ADIS16227 데이터 시트보기 (PDF) - Analog Devices
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ADIS16227 Datasheet PDF : 24 Pages
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ADIS16227
Data Sheet
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Parameter
Description
Min1
Typ
Max
Unit
fSCLK
SCLK frequency
0.01
2.25
MHz
tSTALL
Stall period between data, between 16th and 17th SCLK
15.4
µs
tCS
Chip select to SCLK edge
48.8
ns
tDAV
DOUT valid after SCLK edge
100
ns
tDSU
DIN setup time before SCLK rising edge
24.4
ns
tDHD
DIN hold time after SCLK rising edge
48.8
ns
tSR
tSF
tDF, tDR
tSFS
SCLK rise time
SCLK fall time
DOUT rise/fall times
CS high after SCLK edge
E 1 Guaranteed by design, not tested.
Timing Diagrams
12.5
12.5
5
12.5
5
T CS
E SCLK
L DOUT
O DIN
tCS
1
MSB
R/W
tSR
tSF
2
3
4
5
6
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A6
A5
A4
A3
A2
Figure 2. SPI Timing and Sequence
15
16
tSFS
DB2
DB1
LSB
D2
D1
LSB
S CS
OB SCLK
tSTALL
Figure 3. DIN Bit Sequence
ns
ns
ns
ns
Rev. B | Page 4 of 24
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