ADJD-S311-CR999 데이터 시트보기 (PDF) - Avago Technologies
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ADJD-S311-CR999 Datasheet PDF : 20 Pages
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Mechanical Drawing
Note:
1. Dimensions are in milimeters (mm)
2. Standard tolerances (unless otherwise specified)
a. Linear tolerance = +/-0.1mm
b. Angular tolerance = +/-1°
Pin Configuration
1
2
3
A DVDD SCKSLV AVDD
B CLKIO SDASLV SLEEP
C DGND RESET AGND
Dimensions
Description
Package Body Dimension X
Package Body Dimension Y
Package Height
Ball Diameter
Total Pin Count
Nominal (um)
2200
2200
760
250
9
Pin Information
Pin Name Type
A1 DVDD Power
A2 SCKSLV Input
A3 AVDD Power
B1 CLKIO Input
B2 SDASLV Input/Output
B3 SLEEP Input
C1 DGND
C2 RESET
Ground
Input
C3 AGND Power
Description
Digital power pin
Serial interface clock pin
Analog power pin
External clock input
Bidirectional data pin. A pull-up resistor should be tied to SDASLV because it goes tri-state to output logic 1
When SLEEP = 1, the device goes into sleep mode. In sleep mode, all analog circuits are powered down and the clock
signal is gated away from the core logic resulting in very low current consumption.
Tie to digital ground
Global, asynchronous, active-low system reset. When asserted low, XRST resets all registers. Minimum reset pulse low
is 1us and must be provided by external circuitry.
Tie to analog ground
12
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