ADL5373-EVALZ_ 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
ADL5373-EVALZ_ Datasheet PDF : 11 Pages
| |||
Preliminary Technical Data
BASIC CONNECTIONS
Refer to the evaluation board schematic for the basic
connections for operating the F-MOD family.
A single power supply of between 4.75 V and 5.5 V is applied to
pins VPS1 and VPS2 and VPS3. All the VPS pins must be
connected to the same potential. Adjacent pins of the same
name can be tied together and decoupled with a 0.1 uF
capacitor. These capacitors should be located as close as possible
to the device.
All the COMM pins should be tied to the same ground plane
through low impedance paths. The exposed paddle on the
under side of the package should also be soldered to a low
impedance ground plane. If multiple ground planes exist on the
circuit board, these should be stitched together with multiple
(typically 9) vias to enhance thermal and electrical
ADL5370/1/2/3/4
performance.
The baseband inputs QBBP, QBBN, IBBP and IBBN must be
driven from a differential source. The nominal drive level of 1.4
Vpp differential (700 mVpp on each pin) should be biased at
500 mV.
A Single–ended Local Oscillator signal should be applied to the
LOIP pin through an ac-coupling capacitor. The recommended
LO drive power is 0 dBm. The LO return pin, LOIN, should be
ac-coupled to ground though a low impedance path.
The RF output is available at the VOUT pin (Pin 7). This pin
must also be ac-coupled. Both LOIP and VOUT have nominal
broadband input and output impedances of 50 Ω and do not
need further external matching.
QBBP
QBBN
IBBN
IBBP
RFPQ
0Ω
RFNQ
0Ω
CFPQ
Open
RTQ
Open
CFNQ
Open
RFNI
RFPI
0Ω
0Ω
CFNI
Open
RTI
Open
CFPI
Open
ON OFF
ENBL SW21
R21
49.9
ENBL
R22
10k
VPOS
1 COMM
2 COMM
3 VPS1
4 VPS1
5 VPS1
VPOS
C12
0.1uF
6 VPS1
Z1
FMOD
Exposed Paddle
VPS5 18
VPS4 17
VPS3 16
VPS2 15
VPS2 14
VOUT 13
GND
CLOP
100pF
LO
CLON
100pF
C16
0.1uF
L12
C15
0
0.1uF
C14
0.1uF
C13
0.1uF
COUT
100pF
L11
0
C11
OPEN
VPOS
VOUT
Figure 5. F-MOD Evaluation Board Schematic.
Rev. PrG | Page 9 of 11
Share Link: 