ADM1069(RevC) 데이터 시트보기 (PDF) - Analog Devices
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ADM1069 Datasheet PDF : 32 Pages
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ADM1069
Parameter
Min
Typ
Standard (Digital Output) Mode (PDO1 to PDO8)
VOH
2.4
VOL
IOL2
ISINK2
RPULL-UP
ISOURCE (VPx)2
VPU − 0.3
0
16
20
Three-State Output Leakage Current
Oscillator Frequency
90
100
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
Input High Current, IIH
−1
Input Low Current, IIL
Input Capacitance
5
Programmable Pull-Down Current, IPULL-DOWN
20
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH
Input Low Voltage, VIL
Output Low Voltage, VOL2
SERIAL BUS TIMING3
Clock Frequency, fSCLK
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Stop Setup Time, tSU;STO
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Input Low Current, IIL
SEQUENCING ENGINE TIMING
State Change Time
2.0
1.3
0.6
0.6
0.6
1.3
0.6
100
5
10
Max Unit Test Conditions/Comments
V
4.5 V
V
0.50 V
20 mA
60 mA
29 kΩ
2
mA
10 μA
110 kHz
VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
VPU to VPx = 6.0 V, IOH = 0 mA
VPU ≤ 2.7 V, IOH = 0.5 mA
IOL = 20 mA
Maximum sink current per PDOx pin
Maximum total sink for all PDOx pins
Internal pull-up
Current load on any VPx pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
VPx pin
VPDO = 14.4 V
All on-chip time delays derived from this clock
V
0.8 V
μA
1
μA
pF
μA
Maximum VIN = 5.5 V
Maximum VIN = 5.5 V
VIN = 5.5 V
VIN = 0 V
VDDCAP = 4.75 V, TA = 25°C, if known logic state
is required
V
0.8 V
0.4 V
IOUT = −3.0 mA
400 kHz
μs
μs
μs
μs
μs
μs
300 ns
300 ns
ns
ns
1
μA
VIN = 0 V
μs
1 At least one of the VH, VPx pins must be ≥ 3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Timing specifications are guaranteed by design and supported by characterization data.
Rev. C | Page 6 of 32
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