ADM706SAN(RevA) 데이터 시트보기 (PDF) - Analog Devices
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ADM706SAN Datasheet PDF : 8 Pages
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ADM706P/R/S/T, ADM708R/S/T
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic ADM706
MR
1
VCC
2
GND
3
PFI
4
PFO
5
WDI
6
NC
RESET
N/A
7 (R/S/T Only)
RESET
WDO
7 (P Only)
8
Pin No.
ADM708
1
2
3
4
5
N/A
6
7
8
N/A
Function
Manual Reset Input. When taken below 0.6 V a RESET is generated. MR can be
driven from TTL, CMOS logic or from a manual reset switch as it is internally
debounced. An internal 70 µA pull-up current holds the input high when floating.
Power Supply Input.
0 V. Ground reference for all signals.
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator.
When PFI is less than 1.25 V, PFO goes low. If unused, PFI should be connected
to GND.
Power Fail Output. PFO is the output from the Power Fail Comparator. It goes
low when PFI is less than 1.25 V.
Watchdog Input. WDI is a three level input. If WDI remains either high or low
for longer than the watchdog timeout period, the watchdog output WDO goes
low. The timer resets with each transition at the WDI input. Either a high-to-low
or a low-to-high transition will clear the counter. The internal timer is also
cleared whenever reset is asserted. The Watchdog Timer is disabled when WDI is
left floating or connected to a three-state buffer.
No Connect.
Logic Output. RESET goes low for 200 ms when triggered. It can be triggered
either by VCC being below the reset threshold or by a low signal on the manual
reset (MR) input. RESET will remain low whenever VCC is below the reset
threshold. It remains low for 200 ms after VCC goes above the reset threshold or
MR goes from low to high. A watchdog timeout will not trigger RESET unless
WDO is connected to MR.
Logic Output. RESET is an active high output suitable for systems which use
active high RESET logic. It is the inverse of RESET.
Logic Output. The Watchdog Output, WDO, goes low if the internal watchdog
timer times out as a result of inactivity on the WDI input. It remains low until
the watchdog timer is cleared. WDO also goes low during low line conditions.
Whenever VCC is below the reset threshold, WDO remains low. As soon as VCC
goes above the reset threshold, WDO goes high immediately.
PIN CONFIGURATIONS
MR 1
8 WDO
VCC 2 ADM706 7 RESET
GND 3
P
6 WDI
PFI
4
TOP VIEW
(Not to Scale)
5
PFO
MR 1
8 WDO
VCC 2 ADM706 7 RESET
GND 3 R/S/T 6 WDI
PFI
4
TOP VIEW
(Not to Scale)
5
PFO
MR 1
8 RESET
VCC 2 ADM708 7 RESET
GND 3 R/S/T 6 NC
PFI
4
TOP VIEW
(Not to Scale)
5
PFO
NC = NO CONNECT
–4–
REV. A
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