ADM708SAN 데이터 시트보기 (PDF) - Analog Devices

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ADM708SAN

3 V, Voltage Monitoring Microprocessor Supervisory Circuits

Analog Devices 

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

MR 1 ADM708R/ 8 RESET

VCC 2 ADM708S/ 7 RESET

GND 3 ADM708T 6 NC

PFI

4

TOP VIEW

(Not to Scale)

5

PFO

NC = NO CONNECT

Figure 5. ADM708R/ADM708S/ADM708T

Table 4. Pin Function Descriptions ADM708R/ADM708S/ADM708T

Pin No.

Mnemonic Description

1

MR

Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven from TTL, CMOS

logic, or from a manual reset switch because it is internally debounced. An internal 70 μA pull-up current holds

the input high when floating.

2

VCC

Power Supply Input.

3

GND

Ground. Ground reference for all signals (0 V).

4

PFI

Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than 1.25 V, PFO

goes low. If unused, PFI should be connected to GND.

5

PFO

Power-Fail Output. PFO is the output from the power-fail comparator. It goes low when PFI is less than 1.25 V.

6

NC

No Connect.

7

RESET

Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by VCC being below the reset

threshold or by a low signal on the MR input. RESET remains low whenever VCC is below the reset threshold. It

remains low for 200 ms after VCC goes above the reset threshold or MR goes from low to high. A watchdog

timeout does not trigger RESET unless WDO is connected to MR.

8

RESET

Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is the

inverse of RESET.

Rev. C | Page 7 of 16

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