ADN2819(RevC) 데이터 시트보기 (PDF) - Analog Devices

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ADN2819
(Rev.:RevC)

Multirate to 2.7 Gbps Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

Data Sheet

ADN2819

ADN2819

PIN

+

QUANTIZER

0

NIN

50Ω 50Ω

VREF

1

50Ω 50Ω

FROM

QUANTIZER

OUTPUT

1

CDR

RETIMED

DATA

CLK

0

VCC

TDINP/N

LOOPEN BYPASS DATAOUTP/N

Figure 21. Test Modes

CLKOUTP/N SQUELCH

SQUELCH MODE

When the squelch input is driven to a TTL high state, the clock

and data outputs are set to the zero state to suppress down-

stream processing. If desired, this pin can be directly driven by

the LOS (loss of signal) detector output (SDOUT). If the

squelch function is not required, the pin must be tied to VEE.

TEST MODES: BYPASS AND LOOPBACK

When the bypass input is driven to a TTL high state, the

quantizer output is connected directly to the buffers driving the

data out pins, thus bypassing the clock recovery circuit (see

Figure 21). This feature can help the system deal with

nonstandard bit rates.

The loopback mode can be invoked by driving the LOOPEN

pin to a TTL high state, which facilitates system diagnostic

testing. This connects the test inputs (TDINP/N) to the clock

and data recovery circuit (per Figure 21). The test inputs have

internal 50 Ω terminations, and can be left floating when not in

use. TDINP/N are CML inputs and can only be dc-coupled

when being driven by CML outputs. The TDINP/N inputs must

be ac-coupled if driven by anything other than CML outputs.

Bypass and loopback modes are mutually exclusive: only one of

these modes can be used at any given time. The ADN2819 is

put into an indeterminate state if both the BYPASS and

LOOPEN pins are set to Logic 1 at the same time.

Rev. C | Page 17 of 25

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