ADP3120 데이터 시트보기 (PDF) - Analog Devices
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ADP3120 Datasheet PDF : 16 Pages
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ADP3120
The MOSFET vendor should provide a maximum voltage slew
rate at drain current rating such that this can be designed around.
Once this specification is obtained, determine the maximum
current expected in the MOSFET. This can be done with the
following equation:
( ) I MAX = IDC ( per phase) + VCC −VOUT
× DMAX (5)
f MAX × LOUT
where:
DMAX is determined for the VR controller being used with
the driver. This current is divided roughly equally between
MOSFETs if more than one is used (assume a worst-case
mismatch of 30% for design margin).
LOUT is the output inductor value.
When producing the design, there is no exact method for
calculating the dV/dt due to the parasitic effects in the external
MOSFETs as well as the PCB. However, it can be measured to
determine if it is safe. If it appears that the dV/dt is too fast, an
optional gate resistor can be added between DRVH and the
high-side MOSFETs. This resistor slows down the dV/dt, but it
increases the switching losses in the high-side MOSFETs. The
ADP3120 has been optimally designed with an internal drive
impedance that works with most MOSFETs to switch them
efficiently, yet minimizes dV/dt. However, some high speed
MOSFETs may require this external gate resistor depending on
the currents being switched in the MOSFET.
LOW-SIDE (SYNCHRONOUS) MOSFETS
The low-side MOSFETs are usually selected to have a low on
resistance to minimize conduction losses. This usually implies a
large input gate capacitance and gate charge. The first concern is
to make sure the power delivery from the ADP3120 DRVL does
not exceed the thermal rating of the driver (see the ADP3186 or
ADP3188 data sheet for Flex-Mode controller details).
The next concern for the low-side MOSFETs is to prevent
them from being switched on inadvertently when the high-side
MOSFET turns on. This occurs due to the drain-gate (Miller,
also specified as Crss) capacitance of the MOSFET. When the
drain of the low-side MOSFET is switched to VCC by the high-
side turning on (at a dV/dt rate ), the internal gate of the low-
side MOSFET is pulled up by an amount roughly equal to VCC
× (Crss/Ciss). It is important to make sure this does not put the
MOSFET into conduction.
Another consideration is the nonoverlap circuitry of the
ADP3120, which attempts to minimize the nonoverlap period.
During the state of the high-side turning off to low-side turning
on, the SW pin is monitored (as well as the conditions of SW
prior to switching) to adequately prevent overlap.
However, during the low-side turn off to high-side turn on,
the SW pin does not contain information for determining
the proper switching time, so the state of the DRVL pin is
monitored to go below one sixth of VCC. Then a delay is added.
Due to the Miller capacitance and internal delays of the low-
side MOSFET gate, one must ensure that the Miller-to-input
capacitance ratio is low enough and that the low-side MOSFET
internal delays are not so large as to allow accidental turn on of
the low-side when the high-side turns on.
Contact ADI for an updated list of recommended low-side
MOSFETs.
PC BOARD LAYOUT CONSIDERATIONS
Use these general guidelines when designing printed circuit
boards:
• Trace out the high current paths and use short, wide
(>20 mil) traces to make these connections.
• Minimize trace inductance between DRVH and DRVL
outputs and MOSFET gates.
• Connect the PGND pin of the ADP3120 as closely as
possible to the source of the lower MOSFET.
• Locate the VCC bypass capacitor as close as possible to
the VCC and PGND pins.
• Use vias to other layers when possible to maximize
thermal conduction away from the IC.
The circuit in Figure 16 shows how four drivers can be
combined with an ADP3188 to form a total power conver-
sion solution for generating VCC(CORE) for an Intel CPU that is
VRD 10.x-compliant.
Figure 15 shows an example of the typical land patterns based
on the guidelines given previously. For more detailed layout
guidelines for a complete CPU voltage regulator subsystem,
refer to the PC Board Layout Considerations section of the
ADP3188 data sheet.
CBST1
CBST2
RBST
D1
CVCC
Figure 15. External Component Placement Example
Rev. 0 | Page 11 of 16
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