ADP3120 데이터 시트보기 (PDF) - Analog Devices

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ADP3120

Dual Bootstrapped 12 V MOSFET Driver with Output Disable

Analog Devices 

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

ADP3120

BST 1

8 DRVH

IN 2 ADP3120 7 SW

OD 3 TOP VIEW 6 PGND

VCC 4 (Not to Scale) 5 DRVL

Figure 2. 8-Lead SOIC Pin Configuration

BST 1

IN 2

OD 3

VCC 4

PIN 1

INDICATOR

ADP3120

TOP VIEW

(Not to Scale)

8 DRVH

7 SW

6 PGND

5 DRVL

Figure 3. 8-Lead LFCSP Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1

BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this

bootstrapped voltage for the high-side MOSFET as it is switched.

2

IN

Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling this pin

low turns on the low-side driver; pulling it high turns on the high-side driver.

3

OD

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.

4

VCC

Input Supply. This pin should be bypassed to PGND with an ~1 μF ceramic capacitor.

5

DRVL

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.

6

PGND

Power Ground. Should be closely connected to the source of the lower MOSFET.

7

SW

This pin is connected to the buck-switching node, close to the upper MOSFET source. It is the floating return for

the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent the lower MOSFET

from turning on until the voltage is below ~1 V.

8

DRVH

Buck Drive. Output drive for the upper (buck) MOSFET.

Rev. 0 | Page 5 of 16

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