ADP3418 데이터 시트보기 (PDF) - Analog Devices

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ADP3418

Dual Bootstrapped 12 V MOSFET Driver with Output Disable

Analog Devices 

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADP3418

BST 1

8 DRVH

IN 2 AD3418 7 SW

TOP VIEW

OD 3 (Not to Scale) 6 PGND

VCC 4

5 DRVL

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1

BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this

bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be between 100 nF and 1 µF.

2

IN

Logic Level Input. This pin has primary control of the drive outputs.

3

OD

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.

4

VCC

Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.

5

DRVL

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.

6

PGND

Power Ground. Should be closely connected to the source of the lower MOSFET.

7

SW

This pin is connected to the buck switching node, close to the upper MOSFET’s source. It is the floating return for

the upper MOSFET drive signal.

8

DRVH

Buck Drive. Output drive for the upper (buck) MOSFET.

Rev. B | Page 5 of 16

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