ADP7104 데이터 시트보기 (PDF) - Analog Devices
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ADP7104 Datasheet PDF : 25 Pages
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Data Sheet
20 V, 500 mA, Low Noise, CMOS LDO
ADP7104
FEATURES
Input voltage range: 3.3 V to 20 V
Maximum output current: 500 mA
Low noise: 15 μV rms for fixed output versions
PSRR performance of 60 dB at 10 kHz, VOUT = 3.3 V
Reverse current protection
Low dropout voltage: 350 mV at 500 mA
Initial accuracy: ±0.8%
Accuracy over line, load, and temperature
−2% to +1%, TJ = −40°C to +125°C
−1.25% to +1%, TJ = 0°C to +85°C
Low quiescent current (VIN = 5 V), IGND = 900 μA with 500 mA load
Low shutdown current: <40 μA at VIN = 12 V, stable with small
1 μF ceramic output capacitor
7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V,
5 V, and 9 V
Adjustable output from 1.22 V to VIN − VDO
Foldback current limit and thermal overload protection
User programmable precision UVLO/enable
Power-good indicator
8-lead LFCSP and 8-lead SOIC packages
APPLICATIONS
Regulation to noise sensitive applications: ADC, DAC circuits,
precision amplifiers, high frequency oscillators, clocks,
and PLLs
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
GENERAL DESCRIPTION
The ADP7104 is a CMOS, low dropout linear regulator that oper-
ates from 3.3 V to 20 V and provides up to 500 mA of output
current. This high input voltage LDO is ideal for regulation of
high performance analog and mixed signal circuits operating
from 19 V to 1.22 V rails. Using an advanced proprietary archi-
tecture, it provides high power supply rejection, low noise, and
achieves excellent line and load transient response with just a
small 1 μF ceramic output capacitor.
The ADP7104 is available in seven fixed output voltage options
and an adjustable version, which allows output voltages that range
from 1.22 V to VIN − VDO via an external feedback divider.
TYPICAL APPLICATION CIRCUITS
VIN = 8V
CIN +
1µF
ON
OFF
R1
100kΩ
R2
100kΩ
VIN VOUT
SENSE
EN/
UVLO
PG
GND
+ COUT
1µF
VOUT = 5V
RPG
100kΩ
PG
Figure 1. ADP7104 with Fixed Output Voltage, 5 V
VIN = 8V
CIN +
1µF
ON
OFF
R1
100kΩ
R2
100kΩ
VIN VOUT
ADJ
EN/
UVLO
PG
GND
40.2kΩ
+
VOUT
COUT
=
5V
1µF
13kΩ
RPG
100kΩ
PG
Figure 2. ADP7104 with Adjustable Output Voltage, 5 V
The ADP7104 output noise voltage is 15 μV rms and is inde-
pendent of the output voltage. A digital power-good output
allows power system monitors to check the health of the output
voltage. A user programmable precision undervoltage lockout
function facilitates sequencing of multiple power supplies.
The ADP7104 is available in 8-lead, 3 mm × 3 mm LFCSP
and 8-lead SOIC packages. The LFCSP offers a very compact
solution and also provides excellent thermal performance for
applications requiring up to 500 mA of output current in a
small, low-profile footprint.
Rev. I
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