ADSP-21261 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21261

SHARC Embedded Processor

Analog Devices 

ADSP-21261/ADSP-21262/ADSP-21266

Table 6. Pin Descriptions (Continued)

State During and

Pin

Type

After Reset

Function

CLK_CFG1–0 I

Input only

Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 9 for a

description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL multiplier

and divider in the PMCTL register at any time after the core comes out of reset.

RESETOUT O

Output only

Reset Out. Drives out the core reset signal to an external device.

RESET

I/A

TCK

I

Input only

Input only3

Processor Reset. Resets the ADSP-2126x to a known state. Upon deassertion, there is a

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program

execution from the hardware reset vector address. The RESET input must be asserted

(low) at power-up.

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed

low) after power-up or held low for proper operation of the ADSP-2126x.

TMS

I/S

Three-state with Test Mode Select (JTAG). Used to control the test state machine. TMS has a

pull-up enabled 22.5 k internal pull-up resistor.

TDI

I/S

Three-state with Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

pull-up enabled 22.5 k internal pull-up resistor.

TDO

O

Three-state4

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST

I/A

Three-state with Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after

pull-up enabled power-up or held low for proper operation of the ADSP-2126x. TRST has a 22.5 k internal

pull-up resistor.

EMU

O (O/D)

Three-state with Emulation Status. Must be connected to the ADSP-2126x Analog Devices DSP Tools

pull-up enabled product line of JTAG emulators target board connector only. EMU has a

22.5 k internal pull-up resistor.

VDDINT

P

Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s core processor

(13 pins on the BGA package, 32 pins on the LQFP package).

VDDEXT

P

I/O Power Supply. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the LQFP

package).

AVDD

P

Analog Power Supply. Nominally +1.2 V dc and supplies the DSP’s internal PLL (clock

generator). This pin has the same specifications as VDDINT, except that added filtering

circuitry is required. For more information, see Power Supplies on Page 7.

AVSS

G

GND

G

Analog Power Supply Return.

Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).

1 RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.

2 Output only is a three-state driver with its output path always enabled.

3 Input only is a three-state driver, with both output path and pull-up disabled.

4 Three-state is a three-state driver, with pull-up disabled.

Rev. G | Page 12 of 48 | December 2012

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