ADSP-21261 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21261

SHARC Embedded Processor

Analog Devices 

ADSP-21261/ADSP-21262/ADSP-21266

TABLE OF CONTENTS

Summary ............................................................... 1

General Description ................................................. 3

Family Core Architecture ........................................ 3

Memory and I/O Interface Features ........................... 4

Target Board JTAG Emulator Connector .................... 8

Development Tools ............................................... 8

Additional Information .......................................... 9

Related Signal Chains ............................................ 9

Pin Function Descriptions ....................................... 10

Address Data Pins as Flags .................................... 13

Core Instruction Rate to CLKIN Ratio Modes ............ 13

Address Data Modes ............................................ 13

Product Specifications ............................................. 14

Operating Conditions .......................................... 14

Electrical Characteristics ....................................... 14

Package Information ........................................... 15

ESD Caution ...................................................... 15

Maximum Power Dissipation ................................. 15

Absolute Maximum Ratings ................................... 15

Timing Specifications ........................................... 15

Output Drive Currents ......................................... 37

Test Conditions .................................................. 37

Capacitive Loading .............................................. 37

Environmental Conditions .................................... 38

Thermal Characteristics ........................................ 38

144-Lead LQFP Pin Configurations ............................ 39

136-Ball BGA Pin Configurations ............................... 40

Outline Dimensions ................................................ 43

Surface-Mount Design .......................................... 44

Automotive Products .............................................. 45

Ordering Guide ..................................................... 45

REVISION HISTORY

12/12—Rev. F to Rev. G

Corrected Long Word Memory Space in Table 4 in

Memory and I/O Interface Features ...............................4

Updated Development Tools .......................................8

Added section, Related Signal Chains .............................9

Changed the package designator in Figure 36 from BC-136 to

BC-136-1. This change in no way affects form, fit, or function.

See Outline Dimensions ........................................... 43

Updated Ordering Guide .......................................... 45

Rev. G | Page 2 of 48 | December 2012

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