ADSP-BF537 데이터 시트보기 (PDF) - Analog Devices

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ADSP-BF537

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF534/ADSP-BF536/ADSP-BF537

TABLE OF CONTENTS

General Description ................................................. 3

Portable Low Power Architecture ............................. 3

System Integration ................................................ 3

Blackfin Processor Peripherals ................................. 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 5

DMA Controllers .................................................. 8

Real-Time Clock ................................................... 9

Watchdog Timer .................................................. 9

Timers ............................................................... 9

Serial Ports (SPORTs) .......................................... 10

Serial Peripheral Interface (SPI) Port ....................... 10

UART Ports ...................................................... 10

Controller Area Network (CAN) ............................ 11

TWI Controller Interface ...................................... 11

10/100 Ethernet MAC .......................................... 11

Ports ................................................................ 12

Parallel Peripheral Interface (PPI) ........................... 12

Dynamic Power Management ................................ 13

Voltage Regulation .............................................. 14

Clock Signals ..................................................... 14

Booting Modes ................................................... 16

Instruction Set Description ................................... 16

Development Tools ............................................. 17

Designing an Emulator-Compatible Processor Board .. 18

Related Documents ............................................. 18

Pin Descriptions .................................................... 19

Specifications ........................................................ 23

Operating Conditions .......................................... 23

Electrical Characteristics ....................................... 24

Absolute Maximum Ratings .................................. 25

ESD Sensitivity ................................................... 25

Package Information ............................................ 25

Timing Specifications ........................................... 26

Asynchronous Memory Read Cycle Timing ............ 28

Asynchronous Memory Write Cycle Timing ........... 29

External Port Bus Request and Grant Cycle Timing .. 30

SDRAM Interface Timing .................................. 31

External DMA Request Timing ............................ 32

Parallel Peripheral Interface Timing ...................... 33

Serial Ports ..................................................... 36

Serial Peripheral Interface Port—Master Timing ...... 40

Serial Peripheral Interface Port—Slave Timing ........ 41

Universal Asynchronous Receiver-Transmitter (UART)

Ports—Receive and Transmit Timing ................. 42

General-Purpose Port Timing ............................. 43

Timer Cycle Timing .......................................... 44

Timer Clock Timing ......................................... 45

JTAG Test and Emulation Port Timing .................. 46

10/100 Ethernet MAC Controller Timing ............... 47

Output Drive Currents ......................................... 50

Power Dissipation ............................................... 53

Test Conditions .................................................. 54

Capacitive Loading .............................................. 55

Thermal Characteristics ........................................ 58

182-Ball Mini-BGA Pinout ....................................... 59

208-Ball Sparse Mini-BGA Pinout .............................. 62

Outline Dimensions ................................................ 65

Surface Mount Design .......................................... 66

Ordering Guide ..................................................... 66

REVISION HISTORY

7/07—Revision B

For this revision of the data sheet, the ADSP-BF534,

ADSP-BF536, and ADSP-BF537 have been combined into

a single family data sheet. Because of this change, not all

processor features and attributes apply across all products. See

Table 1 on Page 3 for a breakdown of product offerings.

Added Table 10, Maximum Duty Cycle for Input Transient

Voltage ............................................................. 25

Added Universal Asynchronous Receiver-Transmitter (UART)

Ports—Receive and Transmit Timing ......................... 42

Revised Figure 47, Figure 48, and Figure 49 Under

Test Conditions ..................................................... 54

Added 208-Ball Mini BGA Thermal Characteristics on Page 58

and 208-Ball Sparse Mini-BGA Pinout on Page 62.

Rev. B | Page 2 of 68 | July 2006

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