ADSP-BF537BBCZ-5AV 데이터 시트보기 (PDF) - Analog Devices
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ADSP-BF537BBCZ-5AV Datasheet PDF : 68 Pages
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ADSP-BF534/ADSP-BF536/ADSP-BF537
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the Blackfin processor.
Table 2 describes the inputs to the CEC, identifies their names
in the event vector table (EVT), and lists their priorities.
Table 2. Core Event Controller (CEC)
Priority
(0 Is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event Class
Emulation/Test Control
Reset
Nonmaskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General-Purpose Interrupt 7
General-Purpose Interrupt 8
General-Purpose Interrupt 9
General-Purpose Interrupt 10
General-Purpose Interrupt 11
General-Purpose Interrupt 12
General-Purpose Interrupt 13
General-Purpose Interrupt 14
General-Purpose Interrupt 15
EVT Entry
EMU
RST
NMI
EVX
—
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and rout-
ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processor provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writ-
ing the appropriate values into the interrupt assignment
registers (IAR). Table 3 describes the inputs into the SIC and the
default mappings into the CEC.
Table 3. System Interrupt Controller (SIC)
Peripheral Interrupt Event
Default
Mapping
PLL Wakeup
IVG7
DMA Error (Generic)
IVG7
DMAR0 Block Interrupt
IVG7
DMAR1 Block Interrupt
IVG7
DMAR0 Overflow Error
IVG7
DMAR1 Overflow Error
IVG7
CAN Error
IVG7
Ethernet Error (ADSP-BF536 and IVG7
ADSP-BF537 only)
SPORT 0 Error
IVG7
SPORT 1 Error
IVG7
PPI Error
IVG7
SPI Error
IVG7
UART0 Error
IVG7
UART1 Error
IVG7
Real-Time Clock
IVG8
DMA Channel 0 (PPI)
IVG8
DMA Channel 3 (SPORT 0 Rx)
IVG9
DMA Channel 4 (SPORT 0 Tx)
IVG9
DMA Channel 5 (SPORT 1 Rx)
IVG9
DMA Channel 6 (SPORT 1 Tx)
IVG9
TWI
IVG10
DMA Channel 7 (SPI)
IVG10
DMA Channel 8 (UART0 Rx)
IVG10
DMA Channel 9 (UART0 Tx)
IVG10
DMA Channel 10 (UART1 Rx)
IVG10
DMA Channel 11 (UART1 Tx)
IVG10
CAN Rx
IVG11
CAN Tx
IVG11
DMA Channel 1 (Ethernet Rx,
IVG11
ADSP-BF536 and ADSP-BF537 only)
Port H Interrupt A
IVG11
DMA Channel 2 (Ethernet Tx,
IVG11
ADSP-BF536 and ADSP-BF537 only)
Port H Interrupt B
IVG11
Timer 0
IVG12
Timer 1
IVG12
Timer 2
IVG12
Timer 3
IVG12
Timer 4
IVG12
Timer 5
IVG12
Timer 6
IVG12
Timer 7
IVG12
Port F, G Interrupt A
IVG12
Port G Interrupt B
IVG12
Peripheral
Interrupt ID
0
1
1
1
1
1
2
2
2
2
2
2
2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
17
18
18
19
20
21
22
23
24
25
26
27
28
Rev. J | Page 7 of 68 | February 2014
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