ADV7533 데이터 시트보기 (PDF) - Analog Devices
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ADV7533 Datasheet PDF : 12 Pages
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ADV7533
The power supply noise sensitivity of the ADV7533 is frequency dependent. Therefore, the maximum noise limit for the PVDD is
specified in mV rms vs. frequency (see Figure 2).
70
60
50
40
30
20
10
0
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 2. PVDD Maximum Noise Limit
MIPI/DSI SPECIFICATIONS
Unless noted, timing and levels comply with MIPI DPHY standards.
Table 2. DSI High Speed (HS) Specifications
Parameters
DC SPECIFICATIONS
DSI Input Common Mode Voltage
DSI Input High Threshold
DSI Input Low Threshold
DSI Single-Ended Input High Voltage
DSI Single-Ended Input Low Voltage
DSI Single-Ended Threshold for Termination Enable
Differential Input Impedance
AC SPECIFICATIONS
Single Channel Data Rate
Data to Clock Setup Time
Data to Clock Hold Time
DSI Clock Duty Cycle
Common-Mode Interference Beyond 450 MHz
Common-Mode Interference 50 MHz to 450 MHz
Common-Mode Termination
Symbol
VCMRX
VIDTH
VIDTL
VIHHS
VILHS
VTERM-EN
ZID
tSETUP
tHOLD
∆VCMRX(HF)
∆VCMRX(LF)
CCM
Temp Test Level
25°C VII
25°C VII
25°C VII
25°C VII
25°C VII
25°C VII
25°C VII
25°C IV
25°C VII
25°C VII
25°C VII
25°C VII
25°C VII
25°C VII
ADV7533
Min Typ
70
−70
−40
80
100
200
0.15
0.15
45
50
−50
Max Unit
330 mV
70
mV
mV
460 mV
mV
450 mV
125 Ω
800 Mbps
UIINST
UIINST
55
%
100 mV
+50 mV
60
pF
Rev. 0 | Page 6 of 12
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