AG1170 데이터 시트보기 (PDF) - Unspecified

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AG1170

+5V / +3.3V Low Power Ringing SLIC

Unspecified 

V1.9 September 2006

Data Sheet

Ag1170

+5V / +3.3V LOW POWER RINGING SLIC

8.0 Layout Considerations.

8.1 Power and Ground

Figure 7 gives an example of the tracking needed for

the Ag1170. Tracks to the +VPWR and GNDPWR should

be made as thick as possible. To maximise the

performance of the device, signal tracks should be kept

as short as possible. A low impedance (ESR)

capacitor must be used for C2. To reduce DC/DC noise

capacitors up to 10nF may be connected to ground at

Tip and Ring.

PD is a sensitive node. Keep the tracking as short as

possible. Particularly if connecting a transistor to this

pin.

8.2 Impedance

ZT1, ZT2 and ZB are sensitive nodes. Keep the tracks

as short as possible.

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POWER 220uF, 10V (C2)

FILTER Must be low ESR

0.1uF,

16V (C1)

Tracks for +VPWR and +VA, and for

GNDPWR and GNDA are joined at

the input side of the power filter.

20 21

GN DP WR

GN DP WR

F/R

+ VP W R

+ VP W R

SHK

VOU T

ZB

VIN

ZT2

ZT1

GNDA

+VA

89

Pin Names

Bottom View

100uF,

6.3V (C4)

10R0

(R1)

0.1uF,

25V (C3)

1 Tip (A)

Ring (B)

IC

PD

NC

NC

7 RM

Figure 7: Typical Layout

© Silver Telecom 2006

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