AIC1555 데이터 시트보기 (PDF) - Analog Intergrations
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AIC1555 Datasheet PDF : 15 Pages
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AIC1555
100% Duty Cycle Operation
When the input voltage approaches the output
voltage, the converter continuously turns Q2 on. In
this mode, the output voltage is equal to the input
voltage minus the voltage, which is the drop
across Q2.
If input voltage is very close to output voltage, the
switching mode goes from pure PWM mode to
100% duty cycle operation. During this transient
state mentioned above, large output ripple voltage
will appear on output terminal.
Components Selection
Inductor
The inductor selection depends on the operating
frequency of AIC1555. The internal switching
frequency is 500KHz, and the external
synchronized frequency ranges from 500KHz to
1MHz. A higher frequency allows the uses of
smaller inductor and capacitor values. But, higher
frequency results lower efficiency due to the
internal switching loss.
The ripple current ∆IL interrelates with the inductor
value. A lower inductor value gets a higher ripple
current. Besides, a higher VIN or VOUT can also
get the same result. The inductor value can be
calculated as the following formula.
L
=
1
(f )(∆IL
) VOUT 1−
VOUT
VIN
(1)
Users can define the acceptable ∆IL to gain a
suitable inductor value.
Since AIC1555 can be used in ceramic capacitor
application, the component selection will be
different from the one for the application above.
AIC1555 has a built-in slope compensation, which
acitvates when duty cycle is larger than 0.45. The
μ slope Ma, 0.27V/ s, has to be larger than half of
M2. M2 is equal to output voltage divided by L1.
The formula of inductor is shown as below:
L1 > VOUT = VOUT
(2)
2 × Ma 2 × 0.27
Note that output voltage can be defined according
to user’s requirement to get a suitable inductor
value.
Output Capacitor
The selection of output capacitor depends on the
suitable ripple voltage. Lower ripple voltage
corresponds to lower ESR (Equivalent Series
Resistor) of output capacitor. Typically, once the
ESR is satisfied with the ripple voltage, the value
of capacitor is adequate for filtering. The formula
of ripple voltage is as below:
∆VOUT
=
∆IL ESR +
1
8fCOUT
(3)
Besides, in buck converter architecture frequency
√ stands at 1/ (LC) when a double pole formed by
the inductor and output capcitor occurs. This will
reduce phase margin of circuit so that the stability
gets weakened. Therefore, a feedforward
capacitor that is parallel with R1 can be added to
reduce output ripple voltage and increase circuit
stability. The output capacitor can be calculated as
the following formula.
1
1
≅
(4)
L1× CO R1× CF
For more reduction in the ripple voltage, a 12pF
ceramic capacitor, which is parallel with output
capacitor, is used.
External Schottky Diode
AIC1555 has an internal synchronous rectifier,
instead of Schottky diode in buck converter.
However, a blank time, which is an interval when
both of main switch, Q2, and synchronous rectifier,
Q3, are off; occurs at each switching cycle. At the
moment, AIC1555 has a decreasing efficiency.
Therefore, an external Schottky diode is needed to
reinforce the efficiency.
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