MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1-of-10 Decoder
High–Performance Silicon–Gate CMOS
The MC74HC42 is identical in pinout to the LS42. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The HC42 decodes a BCD Address to one–of–ten active low outputs. For
Address inputs with a hexadecimal equivalent greater than 9, all outputs,
Y0 – Y9, remain high (inactive).
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 104 FETs or 26 Equivalent Gates
LOGIC DIAGRAM
15
A0
(LSB)
BCD
ADDRESS
INPUTS
14
A1
13
A2
12
A3
(MSB)
PIN 16 = VCC
PIN 8 = GND
1
Y0
2
Y1
3
Y2
4
Y3
5
Y4
6
Y5
7
Y6
9
Y7
10
Y8
11
Y9
ACTIVE LOW
OUTPUTS
MC74HC42
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC74HCXXN
MC74HCXXD
Plastic
SOIC
PIN ASSIGNMENT
Y0 1
Y1 2
Y2 3
Y3 4
Y4 5
Y5 6
Y6 7
GND 8
16 VCC
15 A0
14 A1
13 A2
12 A3
11 Y9
10 Y8
9 Y7
10/95
© Motorola, Inc. 1995
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