AIC1880 데이터 시트보기 (PDF) - Analog Intergrations
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AIC1880 Datasheet PDF : 11 Pages
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AIC1880
VOUT
= 1.24 × ⎜⎜⎝⎛1+
R1
R2
⎟⎟⎠⎞
The resistive divider should sit as close to FB pin as
possible.
Loop Compensation
In order to avoid the poor output voltage ripple and low
efficiency caused by instability, AIC1880 requires a
proper external compensation network to compensate
its feedback loop. In this external compensation net-
work, RCOMP is used to set the high-frequency integra-
tor gain for fast transient response. While RCOMP is de-
cided, CCOMP is chosen to set the integrator zero to
maintain the loop stability. CCOMP2 is used to cancel the
zero caused by the output capacitor and its ESR. While
using the ceramic capacitor as the output capacitor,
CCOMP2 can be omitted due to the small ESR.
( ) RCOMP ≅ 10 ×
COUT × VOUT kΩ
L
VIN
( ) CCOMP
≅
RL ⋅ COUT
10 × RCOMP
F
( ) CCOMP2
≅
ESR × COUT
R COMP
F
For each components of external compensation net-
work, the above equations provide the approximate
calculations. In order to obtain better transient per-
formance, it is necessary to adjust the component val-
ues of external compensation network.
Layout Consideration
In order to ensure a proper operation of AIC1880, the
following points should be managed comprehensively.
1. The input capacitor and VIN should be placed as
close as possible to each other to reduce the input
ripple voltage.
2. The output loop, which is consisted of the inductor,
the internal power switch, the Schottky diode and
the output capacitor, should be kept as small as
possible.
3. The routes with large current should be kept short
and wide.
4. Logically the large current on the converter should
flow at the same direction.
5. The FB pin should be connected to the feedback
resistors directly and the route should be away
from the noise sources.
6. The soft-start capacitor should be connected to the
SS pin and GND pin directly.
9
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