AK5354VT 데이터 시트보기 (PDF) - Asahi Kasei Microdevices

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AK5354VT

Low Power 20bit ∆Σ ADC with PGA

Asahi Kasei Microdevices 

ASAHI KASEI

„ Timing Diagram

MCLK

LRCK

BCLK

1/fCLK

tCLKH

tCLKL

1/fs

tBLK

tBLKH

tBLKL

Figure 1. Clock Timing

[AK5354]

VIH

VIL

VIH

VIL

VIH

VIL

LRCK

BCLK

SDTO

tBLR

tDLR

tDSS

D20 (MSB)

Figure 2. Audio Data Input/Output Timing (Audio I/F = No.0)

VIH

VIL

VIH

VIL

50%VD

CSN

CCLK

CDTI

tCSS

tCCKL tCCKH

tCDS tCDH

op0

op1

op2

Figure 3. WRITE Command Input Timing

VIH

VIL

VIH

VIL

A0

VIH

VIL

MS0054-E-02

-7-

2004/12

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