AK5352-VF 데이터 시트보기 (PDF) - Asahi Kasei Microdevices

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AK5352-VF

96kHz Sampling ∆Σ 20bit ADC

Asahi Kasei Microdevices 

ASAHI KASEI

21 SDATA

22 CMODE

23 SMODE1

15 SMODE2

24 VB

[AK5352]

O Serial Data Output pin

Data are output with MSB first, in 2's complement format.

After 20 bits are output it turns to "L". It also remains "L" at a

power-down mode(PD="L").

I Master Clock Selection pin

"L": MCLK=256fs

"H": MCLK=384fs

I Serial Interface Mode Select pin

I

Defines the directions of LRCK, SCLK and FSYNC pins and

Output Data Format. SMODE2 is pull-down pin.

SMODE1 SMODE2

MODE

LRCK

L

L

Slave mode: MSB justified : H/L

H

L

Master mode: Similar to I2S : H/L

L

H

Slave mode: I2S

: L/H

H

H

Master mode: I2S

: L/H

- Substrate Power Supply, +5V

0155-E-00

-4-

1997/1

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