AK5352-VF 데이터 시트보기 (PDF) - Asahi Kasei Microdevices
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AK5352-VF Datasheet PDF : 19 Pages
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ASAHI KASEI
[AK5352]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA,VD,VB=5.0V±5%; CL=20pF)
Parameter
Symbol
min
typ
max
Control Clock Frequency
Master Clock 256fs: (fs = ∼98kHz)
fCLK
4.096
12.288
25.088
Pulse width Low
tCLKL
15.9
Pulse width High
384fs: (fs = ∼54kHz)
tCLKH
fCLK
15.9
6.144
18.432
20.736
Pulse width Low
tCLKL
20.83
Pulse width High
tCLKH
20.83
Serial Data Output Clock
fSLK
3.072
6.144
Channel Select Clock(Sampling Frequency)
fs
16
48
98
Duty Cycle
25
75
Serial Interface Timing
(Note 18 )
Slave Mode(SMODE1="L")
SCLK Period
tSLK
159.4
SCLK Pulse width Low
tSLKL
65
Pulse width High
tSLKH
65
SCLK Rising to LRCK Edge (Note 19 )
tSLR
30
LRCK Edge to SCLK Rising (Note 19 )
tLRS
30
LRCK Edge to SDATA MSB Valid
tDLR
50
SCLK Falling to SDATA Valid
tDSS
50
SCLK Rising to FSYNC Edge (Note 19 )
tSF
30
FSYNC Edge to SCLK Rising (Note 19 )
tFS
30
Master Mode(SMODE1="H")
SCLK Frequency
fSLK
64fs
Duty Cycle
50
FSYNC Frequency
fFSYNC
2fs
Duty Cycle
50
SCLK Falling to LRCK Edge
tSLR
-20
20
LRCK Edge to FSYNC Rising
tLRF
1
SCLK Falling to SDATA Valid
tDSS
50
SCLK Falling to FSYNC Edge
tSF
-20
20
Power down timing
PD Pulse width
PD Rising to SDATA Valid
(Note 20 )
tPDW
tPDV
150
516
Note 18 : Refer to Serial Data Interface.
Note 19 : Specified LRCK and FSYNC edges not to coincide with the rising edges of SCLK.
Note 20 : The number of LRCK rising edges after PD brought high. The value is in master mode.
In slave mode it becomes one LRCK clock(1/fs) longer.
Unit
MHz
ns
ns
MHz
ns
ns
MHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
Hz
%
ns
tslk
ns
ns
ns
1/fs
0155-E-00
-9-
1997/1
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