ALC202 데이터 시트보기 (PDF) - Unspecified
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ALC202 Datasheet PDF : 29 Pages
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Avance Logic, Inc.
ALC202
14
13:12
11
10:4
3
2
1
0
R DRS (Double Rate S/PDIF)
ALC202 doesn’t support double rate S/PDIF, this bit is always 0.
R/W SPSR[1:0] (S/PDIF Sample Rate)
00: sample rate set to 44.1KHz , Fs[0:3]=0000
01: reserved
10: sample rate set to 48.0KHz , Fs[0:3]=0100 (default)
11: sample rate set to 32.0KHz , Fs[0:3]=1100
R/W LEVEL (Generation Level)
R/W CC[6:0] (Category Code)
R/W PRE (Preemphasis)
0 : None
1: filter preemphasis is 50/15 usec
R/W COPY (Copyright)
0: Not asserted
1: Asserted
R/W /AUDIO (Non-Audio Data type)
0: PCM data 1: AC3 or other digital non-audio data
R PRO (Professional or Consumer format)
0: consumer format 1: professional format
ALC202 supports consumer channel status format, this bit is always 0.
ÊThe consumer channel status block (bit0~bit31):
0
1
2
3
4
5
6
7
PRO=0 /AUDIO COPY PRE
0
0
0
0
8
9
10
11
12
13
14
15
CC0
CC1
CC2
CC3
CC4
CC5
CC6 LEVEL
16
17
18
19
20
21
22
23
0
0
0
0
0
0
0
0
24
25
26
27
28
29
30
31
Fs0
Fs1
Fs2
Fs3
0
0
0
0
Vendor Define Registers:
MX6A
Miscellaneous Control
Default: 0000h
Bit
Type
Function
15:14
Reserved.
13
R/W DAC PCM(n+1) Slot# Select (When DRA=1)
0: PCM(n+1) captured from Slot-10/11. (Default in AC’97 rev2.2)
1: PCM(n+1) captured from Slot-7/8.
12
R/W S/PDIF SourceŒ
0: S/PDIF data is from controller (default)
1: S/PDIF data is from ADC
11:4
Reserved
3
R/W SPDIF Out Volume Control – Mute Bit
0: Normal 1: Clamp SPDIF output data to 0. (Mute)
2:0
R/W SPDIF Out Volume Control – in 6 dB Step Attenuation ·
000: 0dB
001: - 6dB
010: -12dB
…
111: -42dB
ŒThe default source of S/PDIF output is data sent by controller. When this bit is set, S/PDIF data
comes from ALC202’s ADC. To keep data concurrence, software must guarantee the sample rates
in MX32 and MX3A[13:12] are the same. SPCV is no more a validity for S/PDIF configuration. If
- 14 -
Rev0.62
http://www.realtek.com.tw
Preliminary
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