UT8R256K1615TBDCX 데이터 시트보기 (PDF) - Aeroflex UTMC
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UT8R256K1615TBDCX Datasheet PDF : 14 Pages
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VDD1 1
A0
2
A1
3
A2
4
A3
5
A4
6
/E1 7
DQ0 8
DQ1 9
DQ2 10
DQ3 11
VDD2 12
VSS 13
DQ4 14
DQ5 15
DQ6 16
DQ7 17
/W
18
A5
19
A6
20
A7
21
A8
22
A9
23
NC 24
48
NC
47
A17
46
A16
45
A15
44
/G
43 /BHE
42 /BLE
41 DQ15
40 DQ14
39 DQ13
38 DQ12
37 VSS
36 VDD2
35 DQ11
34 DQ10
33 DQ9
32 DQ8
31
E2
30
A14
29
A13
28
A12
27
A11
26
A10
25 VDD1
DEVICE OPERATION
The UT8R256K16 has four control inputs called Enable 1 ( E1),
Enable 2 (E2), Write Enable (W), Half-word Enables (BLE/
BHE) and Output Enable (G); 18 address inputs, A(17:0); and
16 bidirectional data lines, DQ(15:0). E1 and E2 device enables
control device selection, active, and standby modes. Asserting
E1 and E2 enables the device, causes IDD to rise to its active
value, and decodes the 18 address inputs to select one of 262,144
words in the memory. W controls read and write operations.
During a read cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
G W E2 E1 BLE BHE I/O Mode
Mode
XX X H
X
X
DQ(15:8)
Standby
3-State
DQ(7:0)
3-State
Figure 2. 15ns SRAM Pinout
XX L X
X
X DQ(15:8)
3-State
NT PIN NAMES
E A(17:0) Address Input
W Write Enable
DQ(15:0) Data Input/Output
G Output Enable
M E1
Enable (Active Low) VDD1 Power (1.8V)
P E2
Enable (Active High) VDD2 Power (2.5V)
O BHE and Low and high byte
DEVEL BLE
enable
VSS Ground
LH H L
L
LH H L
H
LH H L
L
XL H L
L
XL H L
L
XL H L
H
HH H L
X
DQ(7:0)
3-State
H DQ(15:8)
3-State
DQ(7:0)
Data Out
L DQ(15:8)
Data Out
DQ(7:0)
3-State
L DQ(15:8)
Data Out
DQ(7:0)
Data Out
L DQ(15:8)
Data In
DQ(7:0)
Data In
H DQ(15:8)
3-State
DQ(7:0)
Data In
L DQ(15:8)
Data In
DQ(7:0)
3-State
X DQ(15:8)
DQ(7:0)
All 3-State
IN
XX H L
H
H DQ(15:8)
DQ(7:0)
All 3-State
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
3-State
3-State
2
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