AM186ES-20VIW 데이터 시트보기 (PDF) - InnovASIC, Inc
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AM186ES-20VIW Datasheet PDF : 154 Pages
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IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
Data Sheet
November 15, 2011
TABLE OF CONTENTS
List of Figures ..................................................................................................................................9
List of Tables .................................................................................................................................10
Conventions ...................................................................................................................................13
Acronyms and Abbreviations ........................................................................................................14
1. Introduction...........................................................................................................................15
1.1 General Description.....................................................................................................15
1.2 Features .......................................................................................................................15
2. Packaging, Pin Descriptions, and Physical Dimensions.......................................................16
2.1 Packages and Pinouts ..................................................................................................16
2.1.1 IA186ES TQFP Package ................................................................................17
2.1.2 IA188ES TQFP Package ................................................................................20
2.1.3 TQFP Physical Dimensions ............................................................................23
2.1.4 IA186ES PQFP Package.................................................................................24
2.1.5 IA188ES PQFP Package.................................................................................27
2.1.6 PQFP Physical Dimensions ............................................................................30
2.2 Pin Descriptions ..........................................................................................................31
2.2.1 a19/pio9, a18/pio8, a17/pio7, a16–a0—Address Bus (synchronous
outputs with tristate) .......................................................................................31
2.2.2 ad15–ad8 (IA186ES)—Address/Data Bus (level-sensitive
synchronous inouts with tristate) ....................................................................31
2.2.3 ao15–ao8 (IA188ES)—Address Bus (level-sensitive synchronous
outputs with tristate) .......................................................................................31
2.2.4 ad7–ad0—Address/Data Bus (level-sensitive synchronous inouts with
tristate) ............................................................................................................31
2.2.5 ale—Address Latch Enable (synchronous output) .........................................32
2.2.6 ardy—Asynchronous Ready (level-sensitive asynchronous input) ................32
2.2.7 bhe_n/aden_n (IA186ES only)—Bus High Enable (synchronous
output with tristate)/Address Enable (input with internal pullup) ..................32
2.2.8 clkouta—Clock Output A (synchronous output) ............................................33
2.2.9 clkoutb—Clock Output B (synchronous output) ............................................33
2.2.10 cts0_n/enrx0_n/pio21—Clear-to-Send 0/Enable-Receive-Request 0
(both are asynchronous inputs) .......................................................................33
2.2.11 den_n/ds_n/pio5—Data Enable /Data Strobe (both are synchronous
outputs with tristate) .......................................................................................34
2.2.12 drq0/int5/pio12—DMA Request 0 (synchronous level-sensitive
input)/Maskable Interrupt Request 5 (asynchronous edge-triggered
input) ...............................................................................................................34
2.2.13 drq1/int6/pio13—DMA Request 1 (synchronous level-sensitive
input)/Maskable Interrupt Request 6 (asynchronous edge-triggered
input) ...............................................................................................................34
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