IS42G32256 데이터 시트보기 (PDF) - Integrated Silicon Solution
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IS42G32256 Datasheet PDF : 52 Pages
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IS42G32256
Table 2. Pin Descriptions
Symbol
Pin Number
I/O
A0-A9
30-34, 47-51
I
A10/BP
29
I
CAS
26
I
CKE
54
I
CLK
55
I
CS
28
I
DQ0-DQ31
1, 3-4, 6-7, 9-10,
I/O
12-13, 17-18, 20-21, 60-61,
63-64, 68-69, 71-72, 74-75,
77-78, 81-81, 83-84, 97-98, 100
DQM0-DQM3
23-24, 56-57
I/O
DSF
53
RAS
27
I
WE
25
I
VCCQ
Vcc
GNDQ
GND
NC
2, 8, 14, 22, 59, 67, 73, 76, 79
15, 35, 65, 96
5, 11, 19, 62, 70, 82, 99
16, 46, 66, 85
36-45, 52, 58, 86-95
ISSI ®
Name and Function
Address: Row/Column addresses are multi-
plexed on the same pins. Row address: RA0-
RA9 Column address: CA0-CA7
Bank Select Address: Selects bank to be acti-
vated during row address latch time. Selects
bank for read/write during column address latch
time.
Column Address Strobe: Latches column ad-
dresses on the positive going edge of the CLK
with CAS low. Enables column access.
Clock Enable: Masks system clock to freeze
operation from the next clock cycle. CKE should
be enabled at least one clock + tCKS prior to new
command. Disable input buffers for power down
in standby.
System Clock: Active on the positive going
edge to sample all inputs.
Chip Select: Disables or enables device opera-
tion by masking or enabling all inputs except
CLK, CKE and DQMX.
Data Input/Output: Data Inputs/Outputs are
multiplexed on the same pins.
Data Input/Output Mask: Makes data output
Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte Mask-
ing)
Define Special Function: Enables write per bit,
block write and special mode register set.
Row Address Strobe: Latches row addresses
on the positive going edge of the CLK with RAS
low. Enables row access and precharge.
Write Enable: Enables write operation and row
precharge.
Supplies voltage for data output
Power Supply Voltage
Ground for DQ
Ground
No connect
4
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
09/10/98
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