IS42G32256-7PQ 데이터 시트보기 (PDF) - Integrated Silicon Solution
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IS42G32256-7PQ Datasheet PDF : 52 Pages
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IS42G32256
ISSI ®
Table 5. SGRAM vs SDRAM
SDRAM Function
MRS
Bank Active
Write
DSF
L
H
L
H
L
H
SGRAM Function
MRS SMRS
Bank Active Bank Active
Normal Block
with
with
Write Write
Write per bit Write per bit
Disable
Enable
Notes:
1. If DSF is low, SGRAM functionality is identical to SDRAM functionality.
2. SGRAM can be used as a unified memory by the appropriate DSF control; SGRAM = Graphic Memory + Main Memory.
Table 6. Mode Register Field Table to Program Modes
Register Programmed with MRS
Address
Function
A10
RFU(1)
A9
W.B.L.(2)
A8, A7
TM
A6, A5, A4
CAS Latency
A3
A2, A1, A0
BT
Burst Length
Test Mode
CAS Latency
A8 A7
Type
0 0 Mode Register Set
01
Vendor
10
Use
11
Only
Write Burst Length
A9
Length
0
Burst
1
Single Bit
A6 A5 A4
000
001
010
011
100
101
110
111
Latency
Reserved
—
2
3
Reserved
Reserved
Reserved
Reserved
Burst Type
Burst Length
A3
Type A2 A1 A0
0 Sequential 0 0 0
1 Interleave 0 0 1
010
011
BT=0
1
2
4
8
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 256(Full)(3)
BT=1
Reserved
Reserved
4
8
Reserved
Reserved
Reserved
Reserved
Special mode Register Programmed with SMRS
Address
Function
A10, A9, A8, A7
X
A6
LC(4)
A5
LM(4)
Load Color
A6 Function
0 Disable
1 Enable
Load Mask
A5 Function
0 Disable
1 Enable
Notes:
1. RFU (Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256-bit) is available only at Sequential mode of burst type.
4. If LC and LM both high (1), data of mask and color register will be unknown.
A4, A3, A2, A1, A0
X
POWER UP SEQUENCE
1. Apply power and start clock, attempt to maintain DKE = “H” and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 µs.
3. Issue precharge commands for all banks of the devices.
4. Issue two or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Sequence of 4 and 5 may be changed.
The device is now ready for normal operation.
Integrated Silicon Solution, Inc.
7
ADVANCE INFORMATION SR037-0C
09/10/98
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