IS42G32256-7PQ 데이터 시트보기 (PDF) - Integrated Silicon Solution
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IS42G32256-7PQ Datasheet PDF : 52 Pages
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IS42G32256
ISSI ®
DEVICE OPERATIONS
Clock (CLK)
The clock input is used as the reference for all SGRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with
CKE high all inputs are assumed to be in valid state (low
or high) for the duration of setup and hold time around
positive edge of the clock for proper functionality and Icc
specifications.
Clock Enable (CKE)
The clock enable (CKE) gates the clock onto SGRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock suspended
from the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When both banks are in the idle state and CKE goes
low synchronously with clock, the SGRAM enters the
power down mode from the next clock cycle. The SGRAM
remains in the power down mode ignoring the other inputs
as long as CKE remains low. The power down exit is
synchronous as the internal clock is suspended. When
CKE goes high at least “tSS+lCLOCK” before the high
going edge of the clock, then the SGRAM becomes active
from the same clock edge accepting all the input commands.
Bank Select (A10)
This SGRAM is organized as two independent banks of
262,144 words x 32 bits memory arrays. The A10 inputs
are latched at the time of assertion of RAS and CAS to
select the bank to be used for the operation. When A10 is
asserted low, bank A is selected. When A10 is latched
high, bank B is selected. The banks select Al0 is latched
at bank activate, read, write, mode register set and
precharge operations.
Address Inputs (A0-A9)
The 18 address bits are required to decode the 262,144
word locations are multiplexed into ten address input pins
(A0-A9). The 10-bit row address is latched along with RAS
and A10 during bank activate command. The 8-bit column
address is latched along with CAS, WE and A10 during
read or with command.
NOP and Device Deselect
When RAS, CAS and WE are high, The SGRAM performs
no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which
require more than single clock cycle like bank activate,
burst read, auto refresh, etc. The device deselect is also a
NOP and is entered by asserting CS high. CS high disables
the command decoder so that RAS, CAS, WE, DSF and all
the address inputs are ignored.
Power-up
The following sequence is recommended for Power-up:
1. Power must be applied to either CKE and DQM inputs
to pull them high and other pins are NOP condition at
the condition at the inputs before or along with VDD
(and VDDQ) supply.
The clock signal must also be asserted at the same
time.
2. After VDD reaches the desired voltage, a minimum
pause of 200 microseconds is required with inputs in
NOP condition.
3. Both banks must be precharged now.
4. Perform a minimum of two auto refresh cycles to
stabilize the internal circuitry.
5. Perform a Mode Register Set cycle to program the
CAS latency, burst length and burst type as the default
value of mode register is undefined.
At the end of one clock cycle from the mode register set
cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the
outputs will be in high-impedance state. The high-
impedance of outputs is not guaranteed in any other
power-up sequence.
Note: Sequence of 4 and 5 may be changed.
Mode Register Set (MRS)
The mode register stores the data for controlling the
various operating modes of SGRAM. It programs the CAS
latency, burst type, addressing, burst length, test mode
and various vendor specific options to make SGRAM
useful for variety of different applications. The default
value of the mode register is not defined, therefore the
mode register must be written after power up to operate the
SGRAM. The mode register is written by asserting low on
CS, RAS, CAS, WE and DSF (The SGRAM should be in
active mode with CKE already high prior to writing the
mode register). The state of address pins A0-A9 and A10
in the same cycle as CS, RAS, CAS, WE and DSF going low
is the data written in the mode register. One clock cycles
is required to complete the write in the mode register. The
mode register contents can be changed using the same
command and clock cycle requirements during operation
as long as both banks are in the idle state. The mode
register is divided into various fields depending on
functionality. The burst length field uses A0-A2, burst type
Integrated Silicon Solution, Inc.
9
ADVANCE INFORMATION SR037-0C
09/10/98
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