AS5SS256K36(2003) 데이터 시트보기 (PDF) - Austin Semiconductor
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AS5SS256K36 Datasheet PDF : 16 Pages
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Austin Semiconductor, Inc.
SSRAM
AS5SS256K36 &
AS5SS256K36A
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (-55oC to +125oC or -40oC to +85oC)
DESCRIPTION
CLOCK
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
OUTPUT TIMES
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE\ to output valid
OE\ to output in Low-Z
OE\ to output in High-Z
SETUP TIMES
Address
Address status (ADSC\, ADSP\)
Address advance (ADV\)
Byte write enables (BWa\ - BWd\, GW\, BWE\)
Data-in
Chip enable (CE\)
HOLD TIMES
Address
Address status (ADSC\, ADSP\)
Address advance (ADV\)
Byte write enables (BWa\ - BWd\, GW\, BWE\)
Data-in
Chip enable (CE\)
SYMBOL
-8.5
-10
UNITS NOTES
MIN MAX MIN MAX
tKC
10.0
15.0
ns
tKF
100
66 MHz
tKH
3.0
4.0
ns
2
tKL
3.0
4.0
ns
2
tKQ
tKQX
tKQLZ
tKQHZ
tOEQ
tOELZ
tOEHZ
8.5
10.0 ns
3.0
3.0
ns
3
3.0
3.0
ns 3, 4, 5, 6,
5.0
5.0
ns 3, 4, 5, 6,
5.0
5.0
ns
7
0
0
ns 3, 4, 5, 6,
5.0
5.0
ns 3, 4, 5, 6,
tAS
1.8
2.0
tADSS
1.8
2.0
tAAS
1.8
2.0
tWS
1.8
2.0
tDS
1.8
2.0
tCES
1.8
2.0
ns
8, 9
ns
8, 9
ns
8, 9
ns
8, 9
ns
8, 9
ns
8, 9
tAH
0.5
0.5
tADSH
0.5
0.5
tAAH
0.5
0.5
tWH
0.5
0.5
tDH
0.5
0.5
tCEH
0.5
0.5
ns
8, 9
ns
8, 9
ns
8, 9
ns
8, 9
ns
8, 9
ns
8, 9
NOTE:
1. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted.
2. Measured as HIGH above VIH and LOW below VIL.
3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O.
4. This parameter is sampled.
5. Transition is measured +500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough discussion on these
parameters.
7. OE\ is a “Don’t Care” when a byte write enable is sampled LOW.
8. A READ cycle is defined by byte write enables all HIGH or ADSP\ LOW for the required setup and hold times. A WRITE cycle is defined by
at
least one byte write enable LOW and ADSP\ HIGH for the required setup and hold times.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP\ or
ADSC\ is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges
of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP\ or ADSC\ is LOW to
remain enabled.
AS5SS256K36 &
AS5SS256K36A
Rev. 3.5 2/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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