AS5SS256K36 데이터 시트보기 (PDF) - Austin Semiconductor
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AS5SS256K36 Datasheet PDF : 16 Pages
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Austin Semiconductor, Inc.
SSRAM
AS5SS256K36 &
AS5SS256K36A
PIN DESCRIPTION
Pin Number SYMBOL
37
36
32-35, 44-50,
SA0
81, 82, 99,
SA1
100
SA
92 (A version)
43 (3 CE version)
93
BWa\
94
BWb\
95
BWc\
96
BWd\
87
BWE\
88
GW\
89
CLK
98
CE\
92
(3 CE version)
CE2\
TYPE
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must
Input meet the setup and hold times around the rising edge of CLK. Two
different pinouts are available for the TQFP packages.
Input
Input
Input
Input
Input
Input
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold times
around the rising edge of CLK. A byte write enable is LOW for a WRITE
cycle and HIGH for a READ cycle. Bwa\ controls DQa pins and DQPa;
Bwb\ controls DQb pins and DQPb; Bwc\ controls DQc pins and DQPc;
Bwd\ controls DQd pins and DQPd. Parity bits are featured on this
device.
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold items around the rising
edge of CLK.
Global Write: This active LOW input allows a full 36-bit WRITE to occur
independent of the BWE\ and BWx\ lines and must meet the setup and
hold times around the rising edge of CLK.
Clock: CLK registers address, data, chip enable, byte write enables and
burst control inputs on its rising edge. All synchronous inputs must meet
setup and hold times around the clock's rising edge.
Synchronous Chip Enable: This active LOW input is used to enable the
device and conditions the internal use of ADSP\. CE\ is sampled only
when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable the
device and is sampled only when a new external address is loaded.
CE2\ is only available on the 3 CE version.
97
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to enable the
device and is sampled only when a new external address is loaded.
86
OE\
Input
Output Enable: This active LOW, asynchronous input enables the data
I/O output drivers.
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
83
ADV\
Input
external address is loaded. A HIGH on this pin effectively causes wait
states to be generated (no address advance). To ensure use of correct
address during a WRITE cycle, ADV\ must be HIGH at the rising edge of
the first clock after an ADSP\ cycle is initiated.
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
85
ADSC\ Input registered. A READ or WRITE is performed using the new address if
CE\ is LOW. ADSC\ is also used to place the chip into power-down state
when CE\ is HIGH.
AS5SS256K36 &
AS5SS256K36A
Rev. 3.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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