µPD43256B
Write Cycle Timing Chart 2 (CS Controlled)
tWC
Address (Input)
CS (Input)
WE (Input)
I/O (Input)
tAS
High impedance
tCW
tAW
tWP
tWR
tDW
Data In
tDH
High
impedance
Cautions 1. CS or WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite
in phase with output signals.
Remark Write operation is done during the overlap time of a low level CS and a low level WE.
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