TEST CONDITIONS
FINAL
Device
Under
Test
5.0 V
2.7 kΩ
CL
6.2 kΩ
Note:
Diodes are IN3064 or equivalents.
Figure 1. Test Setup
14971G-5
Table 1. Test Specifications
Test Condition
All
Unit
Output Load
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
100
pF
Input Rise and Fall Times
≤ 20
ns
Input Pulse Levels
0.45–2.4
V
Input timing measurement reference
levels
0.8, 2.0
V
Output timing measurement
reference levels
0.8, 2.0
V
SWITCHING TEST WAVEFORM
3V
1.5 V
0V
Input
Note: For CL = 30 pF.
Test Points
1.5 V
Output
2.4 V
0.45 V
2.0 V
2.0 V
Test Points
0.8 V
0.8 V
Input
Output
Note: For CL = 100 pF.
14971G-6
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
Steady
OUTPUTS
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
KS000010-PAL
Am27C040
9