IS62LV256L-15J 데이터 시트보기 (PDF) - Integrated Circuit Solution Inc

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IS62LV256L-15J

32K x 8 LOW VOLTAGE CMOS STATIC RAM

Integrated Circuit Solution Inc 

IS62LV256L

WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)

Symbol Parameter

-15 ns

Min. Max.

-20 ns

-25 ns

Min. Max. Min. Max. Unit

tWC

Write Cycle Time

tSCE

CE to Write End

15 —

10 —

20 —

25 —

ns

13 —

15 —

ns

tAW

Address Setup Time to Write End

10 —

15 —

20 —

ns

tHA

Address Hold from Write End

0

—

0

—

0—

ns

tSA

t (4)

PWE

Address Setup Time

WE Pulse Width

0

—

10 —

0

—

0—

ns

13 —

15 —

ns

tSD

Data Setup to Write End

8

—

10 —

12 —

ns

tHD

t (2)

HZWE

t (2)

LZWE

Data Hold from Write End

WE LOW to High-Z Output

WE HIGH to Low-Z Output

0

—

—7

0

—

0

—

0—

ns

—8

— 10

ns

0

—

0—

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

4. Tested with OE HIGH.

AC WAVEFORMS

WRITE CYCLE NO. 1 (WE Controlled)(1,2)

ADDRESS

CE

WE

DOUT

DIN

tWC

tSCE

tHA

tAW

tPWE

tSA

tHZWE

DATA UNDEFINED

HIGH-Z

tLZWE

tSD

tHD

DATA-IN VALID

6

Integrated Circuit Solution Inc.

SR007-0B

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