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IS27LV020-12W

262,144 x 8 LOW VOLTAGE CMOS EPROM

Integrated Silicon Solution 

IS27LV020

FUNCTIONAL DESCRIPTION

Programming the IS27LV020

Upon delivery, the IS27LV020 has 2,097,152 bits in the

"ONE", or HIGH state. "ZEROs" are loaded into the

IS27LV020 through the procedure of programming.

The programming mode is entered when 12.5V ± 0.25V is

applied to the VPP pin, VCC = 6V, CE and PGM is at VIL, and

OE is at VIH. For programming, the data to be programmed

is applied eight bits in parallel to the data output pins.

The write programming algorithm reduces programming

time by using 100 µs programming pulses followed by a

byte verification to determine whether the byte has been

successfully programmed. If the data does not verify, an

additional pulse is applied for a maximum of 25 pulses.

This process is repeated while sequencing through each

address of the EPROM.

The write programming algorithm programs and verifies at

VCC = 6V and VPP = 12.5V. After the final address is

completed, all byte are compared to the original data with

VCC = 5.25V.

Program Inhibit

Programming of multiple IS27LV020s in parallel with dif-

ferent data is also easily accomplished. Except for CE, all

like inputs of the parallel IS27LV020 may be common. A

TTL low-level program pulse applied to an IS27LV020 CE

input with VPP = 12.5V ± 0.25V, PGM LOW and OE HIGH

will program that IS27LV020. A high-level CE input inhibits

the other IS27LV020 from being programmed.

Program Verify

A verify should be performed on the programmed bits to

determine that they were correctly programmed. The

verify should be performed with OE and CE at VIL, PGM at

VIH, and VPP between 12.25V and 12.75V.

Auto Select Mode

The auto select mode allows the reading out of a binary

code from an EPROM that will identify its manufacturer

and type. This mode is intended for use by programming

equipment for the purpose of automatically matching the

device to be programmed with its corresponding program-

ming algorithm. This mode is functional in the 25°C ± 5°C

ambient temperature range that is required when pro-

gramming the IS27LV020.

To activate this mode, the programming equipment must

force 12.0V ± 0.5V on address line A9 of the IS27LV020.

ISSI®

Two identifier bytes may then be sequenced from the

device outputs by toggling address line A0 from VIL to VIH.

All other address lines must be held at VIL during auto

select mode.

Byte 0 (A0 = VIL) represents the manufacturer code, and

byte 1 (A0 = VIH), the device identifier code. For the

IS27LV020, these two identifier bytes are given in the

Mode Select table. All identifiers manufacturer and device

codes will possess odd parity, with the MSB (DQ7) defined

as the parity bit.

Read Mode

The IS27LV020 has two control functions, both of which

must be logically satisfied in order to obtain data at the

outputs. Chip Enable (CE) is the power control and should

be used for device selection. Assuming that addresses are

stable, address access time (tACC) is equal to the delay

from CE to output (tCE). Output Enable (OE) is the output

control and should be used to get data to the output pins,

independent of device selection. Data is available at the

outputs tOE after the falling edge of OE assuming that CE

has been LOW and addresses have been stable for at

least tACC – tOE.

Standby Mode

The IS27LV020 has a standby mode which reduces the

maximum VCC active current. It is placed in standby mode

when CE is at VCC ± 0.3V. The amount of current drawn in

standby mode depends on the frequency and the number

of address pins switching. The IS27LV020 is specified

with 50% of the address lines toggling at 5 MHz. A

reduction of the frequency or quantity of address lines

toggling will significantly reduce the actual standby cur-

rent.

Integrated Silicon Solution, Inc.

3

EP019-0A

12/19/97

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