MSM54V12222A 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM54V12222A

262,214 Words x 12 Bits FIELD MEMORY

Oki Electric Industry 

OKI Semiconductor

MSM54V12222A

Power-up and Initialization

On Powering up, the device is designed to begin proper operation after at least 100 us after VCC has

stabilized to a value within the range of recommended operating conditions. After this 100 us stabilization

interval, the following initialization sequence must be performed.

Because the read and write address counters are not valid after power-up, a minimum of 80 dummy write

operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW

operation and an RSTR operation, to properly initialize the write and the read address pointer. Dummy

write cycles/RSTW and dummy read cycles/RSTR may occur simultaneously.

If these dummy read and write operations start while VCC and/or the substrate voltage have not stabi-

lized, it is required to perform an RSTR operation plus a minimum of 80 SRCK cycles plus another RSTR

operation, and an RSTW operation plus a minimum of 80 SRCK cycles plus another RSTW operation to

properly initialize read and write address pointers.

Old/New Data Access

There must be minimum delay of 600 SWCK cycles between writing into memory and reading out from

memory if reading from the first field starts with an RSTR operation, before the start of writing the second

field, (before the next RSTW operation), then the data just written in will be read out.

The start of reading out the first field of data may be delayed past the beginning of writing in the second

field of data for as many as 70 SWCK cycles. If the RSTR operation for the first field read-out occurs less

than 70 SWCK cycles after the RSTW operation for the second field write-in, then the internal buffering of

the device assures that the first field will still be read out. The first field of data that is read out while the

second field of data is written is called "old data".

In order to read out "new data", i.e., the second field written in, the delay between an RSTW operation and

an RSTR operation must be at least 600 SRCK cycles. If the delay between RSTW and RSTR operations

is more than 71 but less than 600 cycles, then the data read out will be undetermined. It may be "old data"

or "new" data or a combination of old and new data. Such a timing should be avoided.

Cascade Operation

The MSM5412222A has been designed to allow easy cascading of multiple memory devices, in order to

obtain a higher storage depth or a longer delay than can be achieved with only one memory device.

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