DS2890V 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2890V

1-Wire® Digital Potentiometer

Dallas Semiconductor -> Maxim Integrated 

MASTER MODE

TX

RX

TX

RX

TX

RX

TX

DATA (LSB FIRST)

C3h

<data byte>

C3h

<data byte>

99h

<data byte>

Reset

COMMENTS

Issue Wiper Increment Command

Read new wiper position

Issue Wiper Increment Command

Read new wiper position

Issue Wiper Decrement Command

Read new wiper position

Reset Pulse

DS2890

1-WIRE SIGNALING

The DS2890 requires strict protocols to ensure data integrity. The protocol consists of four types of

signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read

Data. Except for the presence pulse the bus master initiates all these signals. The DS2890 can

communicate at two different speeds, regular speed and Overdrive Speed. If not explicitly set into the

Overdrive mode, the DS2890 will communicate at regular speed. While in Overdrive Mode the fast

timing applies to all waveforms.

The initialization sequence required to begin any communication with the DS2890 is shown in

Figure 14. A Reset Pulse followed by a Presence Pulse indicates the DS2890 is ready to send or receive

data. The bus master transmits (TX) a reset pulse (tRSTL, minimum 480 µs at regular speed, 48 µs at

Overdrive Speed). The bus master then releases the line and goes into receive mode (RX). The 1-Wire

bus is pulled to a high state via the pull-up resistor. After detecting the rising edge on the data contact, the

DS2890 waits (tPDH, 15-60 µs at regular speed, 2-6 µs at Overdrive speed) and then transmits the

Presence Pulse (tPDL, 60-240 µs at regular speed, 8-24 µs at Overdrive Speed). A Reset Pulse of 480 µs or

longer will exit the Overdrive Mode returning the device to regular speed. If the DS2890 is in Overdrive

Mode and the Reset Pulse is no longer than 80 µs the device will remain in Overdrive Mode.

READ/WRITE TIME SLOTS

The definitions of write and read time slots are illustrated in Figure 15 (a-c). The master initiates all time

slots by driving the data line low. The falling edge of the data line synchronizes the DS2890 to the master

by triggering an internal timing circuit. During write time slots, the timing circuit determines when the

DS2890 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the timing circuit

determines how long the DS2890 will hold the data line low. If the data bit is a “1”, the DS2890 will not

hold the data line low at all.

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