DS2890
Figure 14. INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES”
VPULLUP
VPULLUP MIN
VIH MIN
MASTER TX
"RESET PULSE"
MASTER RX "PRESENCE PULSE"
tRSTH
VIL MAX
0V
tRSTL
tR
tPDH
tPDL
RESISTOR
MASTER
DS2890
REGULAR SPEED
480 µs ≤ tRSTL < ∞*
480 µs ≤ tRSTH < ∞**
15 µs ≤ tPDH < 60 µs
60 ≤ tPDL < 240 µs
OVERDRIVE SPEED
48 µs ≤ tRSTL < 80 µs
48 µs ≤ tRSTH < ∞**
2 µs ≤ tPDH < 6 µs
8 ≤ tPDL < 24 µs
* In order not to mask interrupt signaling by other devices on the 1-Wire bus and to prevent a power-
on reset of the parasite powered circuit, tRSTL + tR should always be less than 960 µs.
** Includes recovery time.
Figure 15. READ/WRITE TIMING DIAGRAMS
a) Write-one Time Slot
VPULLUP
VPULLUP MIN
VIH MIN
VIL MAX
0V
RESISTOR
MASTER
tSLOT
tREC
DS2890
Sampling Window
tLOW1
15µs
(OD: 2µs)
(OD: 6µs)
60µs
REGULAR SPEED
60 µs ≤ tSLOT < 120 µs
1 µs ≤ tLOW1 < 15 µs
1 µs ≤ tREC < ∞
OVERDRIVE SPEED
6 µs ≤ tSLOT < 16 µs
1 µs ≤ tLOW1 < 2 µs
1 µs ≤ tREC < ∞
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