AMMC-5040-W10 데이터 시트보기 (PDF) - Avago Technologies
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AMMC-5040-W10 Datasheet PDF : 10 Pages
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Biasing and Operation
The recommended DC bias condition for the AMMC-5040
is with all four drains connected to a single 4.5V supply and
all four gates connected to an adjustable negative voltage
supply as shown in Figure 15. The gate voltage is adjusted
for a total drain supply current of typically 300 mA. Figures
1–12 can be used to help estimate the minimum drain
voltage and current necessary for a given RF gain and
output power.
As shown in Figure 13, the second, third, and fourth stage
DC drain bias lines are connected internally and therefore
require only a single bond wire. An additional bond wire
is needed for the first stage DC drain bias, Vd1.
Only the third and fourth stage DC gate bias lines are
connected internally. A total of three DC gate bond wires
are required: one for Vg1, one for Vg2, and one for the
Vg3/Vg4 connection. The internal matching circuitry at
the RF input creates a 50-ohm DC and RF path to ground.
A blocking capacitor should be used at the RF input. Any
DC voltage applied to the RF input must be maintained
below 1V. The RF output is AC coupled. No ground bond
wires are needed since the ground connection is made
by means of plated through via holes to the backside of
the chip.
Frequency Multiplier Biasing and Operation
The AMMC-5040 can also be used as a frequency doubler,
tripler or quadrupler.
As a frequency doubler, the AMMC-5040 provides
conversion gain for input signals in the 10–23 GHz frequen-
cy range for output frequencies of 20–46 GHz. Similarly,
5–10 GHz signals can be quadrupled up to 20–40 GHz with
some conversion loss.
Optimum conversion efficiency as a doubler is obtained
with an input power level of 3–8 dBm. For use as a fre-
quency tripler, an input power level of 14–16 dBm is
recommended.
Frequency multiplication is achieved by reducing the bias
on the first stage FET to efficiently generate harmonics.
The remaining three stages are then used to provide
amplification.
While many bias schemes may be used to generate and
amplify the desired harmonics within the AMMC-5040,
the following information is suggested as a starting point
for multiplier applications.
Frequency doubling or quadrupling (generation of even
harmonics) is accomplished by biasing the first stage FET
at pinch-off by setting Vg1 = Vp ≈ -1.1 volts. The remain-
ing three stages are biased for normal amplification, e.g.,
Vgg is adjusted such that Id2 + Id3 + Id4 ≈ 250 mA. The
drain voltage, Vdd, for all four stages should be 3.5 – 4.5
volts. The assembly diagram shown in Figure 16 can be
used as a guideline.
To operate the AMMC-5040 as a frequency tripler (odd
harmonic), the device is biased as shown in Figure 17. The
drain voltage for the first stage FET is biased separately
with Vd1 reduced to 1.1 - 1.2 volts. The drain voltage for
the remaining three stages, Vd2, Vd3, and Vd4, should
be 3.5 - 4.5 volts. All four gate voltages, Vgg, are set to
approximately –0.6 volts. If desired, Vgg can be adjusted
to minimize second harmonics. Improved multiplier per-
formance can be obtained by biasing both the gate and
drain voltages for the first stage separately from stages
2 – 4.
In all cases, Cb > 100 nF to assure stability.
Assembly Techniques
The chip should be attached directly to the ground plane
using electrically conductive epoxy [1]. For conductive
epoxy, the amount should be just enough to provide a
thin fillet around the bottom perimeter of the die. The
ground plane should be free of any residue that may
jeopardize electrical or mechanical attachment. Caution
should be taken to not exceed the Absolute Maximum
Rating for assembly temperature and time.
Thermo-sonic wedge bonding is the preferred method
for wire attachment to the bond pads. The RF connections
should be kept as short as possible to minimize induc-
tance. 0.7mil gold wire is recommended. The recom-
mended wire bonding stage temperature is 150±2˚C.
The chip is 100μm thick and should be handled with
care.
This MMIC has exposed air bridges on the top surface.
Handle at the edges or with a custom collet (do not pick
up die with vacuum on die center).
This MMIC is also static sensitive and ESD handling pre-
cautions should be taken.
For more detailed information, see Avago Application
Note 54 “GaAs MMIC ESD, Die Attach and Bonding Guide
lines.”
Notes:
1. Sumitomo 1295SA silver epoxy is recommended.
2. Eutectic attach is not recommended and may jeopardize reliability
of the device.
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