AN101 데이터 시트보기 (PDF) - Vishay Semiconductors
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AN101 Datasheet PDF : 5 Pages
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AN101
In Figure 4, consider the case where VDS = 0 and where
a negative voltage VGS is applied to the gate. Again, a
depletion layer has built up. If a small value of VDS were
now applied, this depletion layer would limit the resultant
channel current to a value lower than would be the case
for VGS = 0. In fact, at a value of VGS > VP the channel
current would be almost entirely cut off. This cutoff volt-
age is referred to as the gate cutoff voltage, and may be
expressed by the symbol VP or by VGS(off). VP has been
widely used in the past, but VGS(off) is now more com-
monly accepted since it eliminates the ambiguity be-
tween gate cut-off and drain pinch-off.
saturation region. JFETs operating in the current satura-
tion region make excellent amplifiers. Note that in the
ohmic region both VGS and VDS control the channel cur-
rent, while in the current saturation region VDS has little
effect and VGS essentially controls ID.
Figure 5b relates the curves in Figure 5a to the actual cir-
cuit arrangement, and shows the number of meters which
may be connected to display the conditions relevant to
any combination of VDS and VGS. Note that the direction
of the arrow at the gate gives the direction of current flow
for the forward-bias condition of the junction. In practice,
however, it is always reverse-biased.
Depletion
Layer
The p-channel JFET works in precisely the same way as
S
D
the n-channel JFET. In manufacture, the planar process is
P
N
VGS
essentially reversed, with the acceptor impurity diffused
first onto n-type silicon, and the donor impurity diffused
later to form a second n-type region and leave a p-type
P
channel. In the p-channel JFET, the channel current is due
to hole movement, rather than to electron mobility. Con-
G
sequently, all the applied polarities are reversed, along
with their directions and the direction of current flow.
Figure 4. N-Channel FET Showing Depletion Due to
Gate-Source Voltage and VDS = 0
The mechanisms of Figures 3 and 4 react together to pro-
vide the family of output characteristics shown in Figure
5a. The area below the pinch-off voltage locus is known
as the ohmic region: the area above pinch-off is current
In summary, a junction FET consists essentially of a chan-
nel of semiconductor material along which a current may
flow whose magnitude is a function of two voltages, VDS
and VGS. When VDS is greater than VP, the channel cur-
rent is controlled largely by VGS alone, because VGS is ap-
plied to a reverse-biased junction. The resulting gate cur-
rent is extremely small.
VDS = VP – VGS
IDSS
VGS = 0
ID
VGS = –V
0
VDS
VP
VGS(off)
5a) Family of Output Characteristics
for N-Channel FET
Figure 5.
ID
ID
+
D
–
G
VDS
S
–
VGS
+
5b) Circuit Arrangement for N-Channel FET
Siliconix
3
10-Mar-97
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