AN105 데이터 시트보기 (PDF) - Vishay Semiconductors

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AN105

FETs As Voltage-Controlled Resistors

Vishay Semiconductors 

AN105

VGS = 0 V

3

0V

ID 200

D

G

S

–400 –200

VGS = –3.0 V

2

1

–1.5 V

–2.5 V

VGS = –3.0 V

200 400

VDS (mV)

–1.5 V

–2.5 V

5 10

VDS (V)

–3.0 V

–2.5 V

–1.5 V

0V

–200

Siliconix offers a family of n-channel FETs specifically

intended for use as voltage-controlled resistors. These de-

vices have rDS(on) values ranging from 20 W to 4,000 W,

where VCR2N = 20 – 60 W, VCR4N = 200 – 600 W,

VCR7N = 4 k – 8 kW.

Applications for VCRs

A simple application of a FET VCR is shown in Figure 4,

the circuit for a voltage divider attenuator.

R

VIN

VOUT

VCR

–

VGS

+

Figure 2. NĆChannel JFET Output Characteristics

Enlarged Around VDS = 0 V

Figure 4. Simple Attenuator Circuit

The graph in Figure 3 is useful in estimating rDS values

at any given value of VGS. The resistance is normalized

to its specific value at VGS = 0 V. The dynamic range of

rDS is shown as greater than 100:1, although for best con-

trol of rDS a range of 10:1 is normally used.

1000

VDS ¬ 0.1 V

The output voltage is:

VIN rDS

VOUT + R ) rDS

(1)

It is assumed that the output voltage is not so large as to

push the VCR out of the linear resistance region, and that

the rDS is not shunted by the load.

The lowest value which vOUT can assume is:

VIN rDS(on)

VOUT(min) + R ) rDS(on)

(2)

100

Signal Distortion: Causes

rDS(on)

rDS ] 1 – VGSńVGS(off)

10

Figure 2 shows that the bias lines bend down as VDS

increases in a positive direction toward the pinch-off voltage

of the FET. The bending of the bias lines results in a change

in rDS, and hence the distortion encountered in VCR circuits;

note that the distortion occurs in both the first and third

quadrants. Distortion results because the channel depletion

layer increases as VDS reduces the drain current so that a

1

0

0.2

0.4

0.6

0.8

1.0

pinch-off condition is reached when VDS = VGS – VGS(off).

Figure 5 shows how the current has an opposite effect in the

VGS/VGS(off)

third quadrant, increasing negatively with an increasingly

Figure 3. Normalized rDS Data

negative VDS. This is due to the forward conduction of the

gate-to-channel junction when the drain signal exceeds the

negative gate bias voltage.

2

Siliconix

10-Mar-97

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