AN2104 데이터 시트보기 (PDF) - Freescale Semiconductor

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AN2104

Using Background Debug Mode for the M68HC12 Family

Freescale Semiconductor 

Application Note

Freescale Semiconductor, Inc.

BDM Registers

Seven BDM registers are mapped into addresses $FF00–$FF06. See

Table 3.

NOTE: Remember that the BDM firmware ROM and registers contain different

data than the normal memory mapped locations for these addresses.

Address

$FF00

$FF01

$FF02–$FF03

$FF04–$FF05

$FF06

Table 3. BDM Registers

Register

BDM instruction register

BDM status register

BDM shift register

BDM address register

BDM CCR holding register

Mnemonic

INSTRUCTION

STATUS

SHIFTER

ADDRESS

CCRSAV

Only two registers are discussed here:

• BDM status register (STATUS)

• BDM CCR (condition code register) holding register (CCRSAV)

The BDM status register can be read at any time, but must not be written

to during BDM operation. See Figure 3 for a description of the bits.

Address: $FF01

Bit 7

6

5

4

3

2

1

Bit 0

Read:

ENBDM EDMACT ENTAG SDV TRACE

0

0

0

Write:

Reset: 0

0

0

0

0

0

0

0

Single-Chip

Peripheral:

1

0

0

0

0

0

0

0

Figure 3. BDM Status Register (STATUS)

This register can be read or written by BDM commands or firmware.

ENBDM — Enable BDM Bit (permit active background debug mode)

0 = BDM cannot be made active (hardware commands still

allowed).

1 = BDM can be made active to allow firmware commands.

AN2104

6

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