AN1672 데이터 시트보기 (PDF) - ON Semiconductor
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AN1672 Datasheet PDF : 10 Pages
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AN1672/D
Section 2: Translation from Different ECL Operating Mode Drivers to Non ECL Receivers
The following table indicates the options available for translation from different ECL operating drivers to non ECL receivers.
Table 4. Translation from Different ECL Operating Mode Drivers to Non ECL Receivers
From:
PECL
VCC = +5 V
LVPECL
VCC = +3.3 V
To:
TTL
VCC = +5 V
H350
H607
ELT21
ELT23
ELT28*
ELT21
ELT23
LVTTL/LVCMOS
VCC = 3.3 V
LVEL92 + LVELT23
or EPT21
or EPT23
or LVELT23
or EPT26
EPT21
EPT23
LVELT23
EPT26
CMOS
VDD = 5 V
PECL to TTL or PECL to LVTTL/LVCMOS
Translator and HCT or ACT
LVPECL to LVTTL Translator and
HCT or ACT Input
LVNECL
VEE = −3.3 V
NECL
VEE = −4.5 to −5.2 V
ELT25
EPT25*
H125
H601
H603
H605
H680*
H681*
ELT25
EPT25*
EPT25
EPT25
LVNECL/TTL Translator to HCT or
ACT Input
NECL/TTL Translator to HCT or
ACT Input
*See text segment for details
From PECL to TTL
MC10H350 as PECL to TTL
Several devices are offered for translation signals from
PECL mode drivers to 5 V supplied TTL receivers. The
MC10H350 operates over the frequency range from DC to
about 50 MHz. Although operation is possible to 80 MHz,
the output will not sustain full spec VOH levels rolling off
with higher frequency.
Open, floating differential inputs on a gate will force the
TTL output to default LOW. By adding a pullup resistor of
1 kW to 4 kW, a device’s output will directly interface with
CMOS (5 V) inputs. The device input pin “common mode
range”, VIHCMR min to max, is insufficient to allow
recognition of LVPECL levels. Single ended operation of
the MC10H350 will require an input signal swing of 700 mV
peak−to−peak or greater.
Outputs are Enabled by Pin 9, OE, going LOW. If left
floating open, MC10H350 Pin 9 will default LOW. Worst
case skew from Output to Output within a device occurs
from Input falling edge to Output falling edge at 125°C at
1.4 ns. For the Input rising edge to Output rising edge, the
worst case skew is about 1 ns (at −55°C). Device to Device
slew is less than 800 ps skew from part to part. Output drive
will come out of saturation with 80 mA − 100 mA, lowering
VOH levels.
MC10H607 / MC100H607 as PECL to TTL
The MC10H607 and MC100H607 are Registered PECL
to TTL translators. A standard output test condition load is
50 pF and 500 W to GND. MR, Pin 19, will default LOW
when floating open, allowing operation. The input pin
“common mode” range is insufficient to allow recognition
of LVPECL levels.
ELT21/23/28 as PECL to TTL
ECL inputs for ELT21/23/28 have 50 kW internal
pulldown resistors. If both ECL ELT21/23 inputs are pulled
below 1.3 V, an override circuit will force the output Q to
HIGH, Qb LOW. By adding an output pullup resistor of 1 to
4 kW, a device will interface with CMOS (5 V) inputs. The
input common mode range for ELT21 / ELT23 is generally
considered to be sufficient (2.2 V) to allow recognition of
PECL HIGH levels (>4 V) allowing translation. Single
ended operation may be accomplished with a VBB reference
voltage placed on the nondriven differential input. If a VBB
pin is present, then it should be bypassed when used or left
floating open when unused. A simple VBB supply may be
created by a resistor divider providing the proper switch
point voltage to preserve duty cycle (see AND8066). A
High Current may be created from a simple buffer gate as
shown in AND8020, Figure 22.
These ELT TTL devices typically display >2X the
required data sheet drive. For example, at VOLmax (0.5 V)
the required sinking drive current is 24 mA and actual drive
>>50 mA. At VOHmin (2.4 V), the spec sourcing drive
current is 3.0 mA and the typical device will source >>8 mA.
The unloaded VOH max may reach as positive as 4.0 V.
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