AOZ1013 데이터 시트보기 (PDF) - Alpha and Omega Semiconductor
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AOZ1013 Datasheet PDF : 14 Pages
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AOZ1013
value and ESR. It can be calculated by the equation
below:
ΔVO
=
ΔIL
×
⎛
⎝
ES
RCO
+
-8----×-----f--1-×-----C-----O--⎠⎞
where,
CO is output capacitor value, and
ESRCO is the equivalent series resistance of the output
capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switch-
ing frequency dominates. Output ripple is mainly caused
by capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
ΔVO = ΔIL × 8-----×-----f--1-×-----C-----O--
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
ΔVO = ΔIL × ESRCO
For lower output ripple voltage across the entire operat-
ing temperature range, X5R or X7R dielectric type of
ceramic, or other low ESR tantalum capacitor or alumi-
num electrolytic capacitor may also be used as output
capacitors.
In a buck converter, output capacitor current is continuous.
The RMS current of output capacitor is decided by the
peak to peak inductor ripple current. It can be
calculated by:
ICO_RMS
=
--Δ----I--L--
12
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the buck inductor is selected to be very small
and inductor ripple current is high, output capacitor could
be overstressed.
Loop Compensation
The AOZ1013 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole and can
be calculated by:
fP1 = -2---π-----×-----C---1-O------×-----R----L-
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
fZ1 = -2---π-----×-----C----O-----1-×----E-----S----R-----C----O--
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter close loop transfer function to get desired gain
and phase. Several different types of compensation
networks can be used for AOZ1013. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1013, FB pin and COMP pin are the inverting
input and the output of internal transconductance error
amplifier. A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
fP2 = -2---π-----×-----C--G--C---E--×--A---G-----V----E---A--
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is compensation capacitor.
The zero given by the external compensation network,
capacitor CC and resistor RC ,is located at:
fZ2 = -2---π-----×-----C---1-C-----×-----R-----C--
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover frequency is also called the converter
bandwidth. Generally a higher bandwidth means faster
response to load transient. However, the bandwidth
should not be too high because of system stability
Rev. 1.2 October 2009
www.aosmd.com
Page 9 of 14
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