AOZ1017 데이터 시트보기 (PDF) - Alpha and Omega Semiconductor
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AOZ1017 Datasheet PDF : 16 Pages
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AOZ1017
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
∆V O
=
∆I
L
×
-------------1-------------
8 × f × CO
If the impedance of ESR at switching frequency domi-
nates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
∆V O = ∆IL × ESRCO
For lower output ripple voltage across the entire
operating temperature range, an X5R or X7R dielectric
type of ceramic, or other low ESR tantalum capacitor
or aluminum electrolytic capacitor may also be used as
output capacitors.
In a buck converter, output capacitor current is continu-
ous. The RMS current of output capacitor is defined by
the peak to peak inductor ripple current. It can be
calculated by:
I CO_RMS = -∆----I---L--
12
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the buck inductor is selected to be very small and
inductor ripple current is high, the output capacitor could
be overstressed.
Schottky Diode Selection
The external freewheeling diode supplies the current to
the inductor when the high side PMOS switch is off. To
reduce the losses due to the forward voltage drop and
recovery of diode, a Schottky diode is recommended.
The maximum reverse voltage rating of the chosen
Schottky diode should be greater than the maximum
input voltage, and the current rating should be greater
than the maximum load current.
Loop Compensation
The AOZ1017 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole and can
be calculated by:
f p1
=
-----------------1------------------
2π × CO × RL
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
fZ1
=
------------------------1-------------------------
2π × CO × ESRCO
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the con-
verter close loop transfer function to get the desired gain
and phase. Several different types of compensation net-
work can be used for the AOZ1017. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1017, FB pin and COMP pin are the inverting
input and the output of internal transconductance error
amplifier. A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
f p2
=
----------------G-----E----A------------------
2π × CC × GVEA
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is compensation capacitor.
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
fZ2
=
-----------------1-------------------
2π × CC × RC
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover frequency is also called the converter
bandwidth. Generally, a higher bandwidth means faster
response to load transient. However, the bandwidth
should not be too high because of system stability
Rev. 1.0 July 2007
www.aosmd.com
Page 10 of 16
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