HM-65162/883 데이터 시트보기 (PDF) - Intersil

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HM-65162/883

2K x 8 Asynchronous CMOS Static RAM

Intersil 

HM-65162/883

Timing Waveforms

ADDRESS

(1) TAVAX

(2) TAVQV

(8) TGHQZ

G

(5) TGLQV

(6) TGLQX

E

(7) TEHQZ

(3) TELQV

(9) TAVQX

Q

NOTE:

1. W is High for a Read Cycle.

(4) TELQX

FIGURE 1. READ CYCLE

Addresses must remain stable for the duration of the read

cycle. To read, G and E must be ≤ VIL and W ≥ VIH. The

output buffers can be controlled independently by G while E

is low. To execute consecutive read cycles, E may be tied

low continuously until all desired locations are accessed.

When E is low, addresses must be driven by stable logic

levels and must not be in the high impedance state.

ADDRESS

E

W

Q

D

(12) TAVWL

(16) TWLQZ

(10) TAVAX

(11) TELWH

(13) TWLWH

(20) TWLEH

(21)

TDVEH

NOTE:

1. G is Low throughout Write Cycle.

(17) TDVWH

(22) TAVWH

FIGURE 2. WRITE CYCLE I

(14) TWHAX

(19) TWHQX

(18) TWHDX

To write, addresses must be stable, E low and W falling low

for a period no shorter than TWLWH. Data in is referenced

with the rising edge of W, (TDVWH and TWHDX). While

addresses are changing, W must be high. When W falls low,

the I/O pins are still in the output state for a period of TWLQZ

and input data of the opposite phase to the outputs must not

be applied, (Bus contention). If E transitions low

simultaneously with the W line transitioning low or after the

W transition, the output will remain in a high impedance

state. G is held continuously low.

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