MT28F642D18FN-704TET 데이터 시트보기 (PDF) - Micron Technology

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MT28F642D18FN-704TET

FLASH MEMORY

Micron Technology 

ADVANCE

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

STATUS REGISTER

The status register allows the user to determine

whether the state of a PROGRAM/ERASE operation is

pending or complete. The status register is monitored

by toggling OE# and CE# and reading the resulting

status code on I/Os DQ0–DQ7. The high-order I/Os

(DQ8–DQ15) are set to 00h internally, so only the low-

order I/Os (DQ0–DQ7) need to be interpreted. Address

lines select the status register pertinent to the selected

memory partition.

Register data is updated and latched on the falling

edge of ADV# or the rising (falling) edge of CLK when

ADV# is LOW during synchronous burst mode, or on

the falling edge of OE# or CE#, whichever occurs last.

Latching the data prevents errors from occurring if the

register input changes during status register monitor-

ing.

The status register provides a reading of the inter-

nal state of the WSM to the external microprocessor.

During periods when the WSM is active, the status reg-

ister can be polled to determine the WSM status. Table

8 defines the status register bits.

After monitoring the status register during a PRO-

GRAM/ERASE operation, the data appearing on

DQ0–DQ7 remains as status register data until a new

command is issued to the CSM. To return the device to

other modes of operation, a new command must be

issued to the CSM.

COMMAND STATE MACHINE

OPERATIONS

The CSM decodes instructions for the commands

listed in Table 3. The 8-bit command code is input to

the device on DQ0–DQ7 (see Table 3 for CSM codes

and Table 4 for command definitions). During a PRO-

GRAM or ERASE cycle, the CSM informs the WSM that a

PROGRAM or ERASE cycle has been requested.

Table 4

Command Definitions

COMMAND

FIRST BUS CYCLE

OPERATION ADDRESS1 DATA

READ ARRAY

WRITE

WA

FFh

READ PROTECTION CONFIGURATION REGISTER

WRITE

IA

90h

READ STATUS REGISTER

WRITE

BA

70h

CLEAR STATUS REGISTER

WRITE

BA

50h

READ QUERY

WRITE

QA

98h

BLOCK ERASE SETUP

WRITE

BA

20h

PROGRAM SETUP

WRITE

WA

40h

ACCELERATED PROGRAMMING ALGORITHM (APA) WRITE

WA

10h

PROGRAM/ERASE SUSPEND

WRITE

BA

B0h

PROGRAM/ERASE RESUME – ERASE CONFIRM

WRITE

BA

D0h

LOCK BLOCK

WRITE

BA

60h

UNLOCK BLOCK

WRITE

BA

60h

LOCK DOWN BLOCK

WRITE

BA

60h

CHECK BLOCK ERASE

WRITE

BA

20h

PROTECTION REGISTER PROGRAM

WRITE

PA

C0h

PROTECTION REGISTER LOCK

WRITE

LPA

C0h

SET READ CONFIGURATION REGISTER

WRITE

RCD

60h

SECOND BUS CYCLE

OPERATION ADDRESS1 DATA

READ

READ

IA

ID

X

SRD

READ

QA

QD

WRITE

BA

D0h

WRITE

WA

WD

WRITE

WA

WD

WRITE

WRITE

WRITE

WRITE

WRITE

WRITE

WRITE

BA

01h

BA

D0h

BA

2Fh

BA

D1h

PA

PD

LPA

FFFDh

RCD

03h

NOTE:

1. WA: Word address of memory location to be

written, or read

IA: Identification code address

BA: Address within the block

ID: Identification code data

SRD: Data read from the status register

QA: Query code address

QD: Query code data

WD: Data to be written at the location WA

PA: Protection register address

PD: Data to be written at the location PA

LPA: Lock protection register address

RCD: Data to be written in the read configuration

register

X: “Don’t Care”

4 Meg x 16 Async/Page/Burst Flash Memory

MT28F642D18_3.p65 – Rev. 3, Pub. 8/02

10

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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