MT28F642D18FN-705TET 데이터 시트보기 (PDF) - Micron Technology

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MT28F642D18FN-705TET

FLASH MEMORY

Micron Technology 

ADVANCE

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

BALL DESCRIPTIONS

59-BALL FBGA

NUMBERS SYMBOL

E8, D8, C8, B8,

A8, B7, A7, C7,

A2, B2, C2, A1,

B1, C1, D2, D1,

D4, B6, A6, C6,

B3, C3

A0–A21

B4

CLK

TYPE

Input

Input

C4

ADV#

Input

A5

VPP

Input

E7

CE#

Input

F8

OE#

Input

C5

WE#

Input

B5

RST#

Input

D6

WP#

Input

F7, E6, E5, G5, DQ0–DQ15

E4, G3, E3, G1,

G7, F6, F5, F4,

D5, F3, F2, E2

D3

WAIT#

Input/

Output

Output

DESCRIPTION

Address Inputs: Inputs for the addresses during READ and WRITE

operations. Addresses are internally latched during READ and WRITE

cycles.

Clock: Synchronizes the Flash memory to the system operating

frequency during synchronous burst mode READ operations. When

configured for synchronous burst mode READs, address is latched on

the first rising (or falling, depending upon the read configuration

register setting) CLK edge when ADV# is active or upon a rising ADV#

edge, whichever occurs first. CLK is ignored during asynchronous

access READ and WRITE operations and during READ PAGE ACCESS

operations.1

Address Valid: Indicates that a valid address is present on the address

inputs. Addresses are latched on the rising edge of ADV# during READ

and WRITE operations. ADV# may be tied active during asynchronous

READ and WRITE operations.1

Program/Erase Enable: [0.9V–2.20V or 11.4V–12.6V] Operates as input

at logic levels to control complete device protection. Provides factory

programming compatibility when driven to 11.4V–12.6V.

Chip Enable: Activates the device when LOW. When CE# is HIGH, the

device is disabled and goes into standby power mode.

Output Enable: Enables the output buffers when LOW. When OE# is

HIGH, the output buffers are disabled.

Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is

LOW, the cycle is either a WRITE to the command state machine (CSM)

or to the memory array.

Reset: When RST# is a logic LOW, the device is in reset mode, which

drives the outputs to High-Z and resets the write state machine (WSM).

When RST# is at logic HIGH, the device is in standard operation. When

RST# transitions from logic LOW to logic HIGH, the device resets all

blocks to locked and defaults to the read array mode.

Write Protect: Controls the lock down function of the flexible locking

feature.

Data Inputs/Outputs: Inputs array data on the second CE# and WE#

cycle during PROGRAM command. Inputs commands to the

command user interface when CE# and WE# are active. DQ0–DQ15

output data when CE# and OE# are active.

Wait: Provides data valid feedback during continuous burst read

access. The signal is gated by OE# and CE#. This signal is always kept at

a valid logic level.

NOTE:

1. The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. The WAIT#

signal can be ignored when operating in asynchronous or page mode, as it is always held at logic “1” or “0,” depending

on the RCR8 setting (see Table 9).

(continued on next page)

4 Meg x 16 Async/Page/Burst Flash Memory

MT28F642D18_3.p65 – Rev. 3, Pub. 8/02

7

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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