MT28F642D20FN-805BET 데이터 시트보기 (PDF) - Micron Technology

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MT28F642D20FN-805BET

FLASH MEMORY

Micron Technology 

ADVANCE

4 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

COMMAND STATE MACHINE (CSM)

Commands are issued to the command state ma-

chine (CSM) using standard microprocessor write tim-

ings. The CSM acts as an interface between external

microprocessors and the internal write state machine

(WSM). The available commands are listed in Table 3,

their definitions are given in Table 4, and their descrip-

tions in Table 5. Program and erase algorithms are au-

tomated by an on-chip WSM. Table 6 shows the CSM

transition states. Once a valid PROGRAM/ERASE com-

mand is entered, the WSM executes the appropriate

algorithm. The algorithm generates the necessary tim-

ing signals to control the device internally and accom-

plish the requested operation. A command is valid only

if the exact sequence of WRITEs is completed. After the

WSM completes its task, the WSM status bit (SR7) is set

to a logic HIGH level (1) (see Table 8), allowing the CSM

to respond to the full command set again.

OPERATIONS

Device operations are selected by entering a stan-

dard JEDEC 8-bit command code with conventional mi-

croprocessor timings into an on-chip CSM through I/Os

DQ0–DQ7. The number of bus cycles required to acti-

vate a command is typically one or two. The first opera-

tion is always a WRITE. Control signals CE#, ADV#, and

WE# must be at a logic LOW level (VIL), and OE# and RST#

must be at logic HIGH (VIH). The second operation, when

needed, can be a WRITE or a READ depending upon the

command. During a READ operation, control signals

CE#, ADV#, and OE# must be at a logic LOW level (VIL),

and WE# and RST# must be at logic HIGH (VIH).

Table 7 illustrates the bus operations for all the

modes: write, read, reset, standby, and output disable.

When the device is powered up, internal reset cir-

cuitry initializes the chip to a read array mode of opera-

tion. Changing the mode of operation requires that a

command code be entered into the CSM. For each of

the memory partitions, an on-chip status register is

available. These two registers enable the progress of

various operations that take place on a memory bank

to be monitored. Either of the two status registers is

interrogated by entering a READ STATUS REGISTER

command onto the CSM (cycle 1), specifying an ad-

dress within the memory partition boundary, and read-

ing the register data on I/Os DQ0–DQ7 (cycle 2). Status

register bits SR0–SR7 correspond to DQ0–DQ7 (see

Table 8).

COMMAND DEFINITION

Once a specific command code has been entered,

the WSM executes an internal algorithm, generating

the necessary timing signals to program, erase, and

verify data. See Table 4 for the CSM command defini-

tions and data for each of the bus cycles.

Table 3

Command State Machine Codes For Device Mode Selection

COMMAND DQ0–DQ7

10h

20h

40h

50h

60h

60h

70h

90h

98h

B0h

C0h

D0h

D1h

FFh

CODE ON DEVICE MODE

Accelerated programming algorithm (APA)

Block erase setup

Program setup

Clear status register

Protection configuration setup

Set read configuration register

Read status register

Read protection configuration register

Read query

Program/erase suspend

Protection register program/lock

Program/erase resume – erase confirm

Check block erase confirm

Read array

4 Meg x 16 Async/Page/Burst Flash Memory

MT28F642D18_3.p65 – Rev. 3, Pub. 8/02

9

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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