MT28F320A18FF-70BET 데이터 시트보기 (PDF) - Micron Technology

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MT28F320A18FF-70BET

FLASH MEMORY

Micron Technology 

PRELIMINARY

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

COMMAND STATE MACHINE

Commands are issued to the command state

machine (CSM) using standard microprocessor write

timings. The CSM acts as an interface between exter-

nal microprocessors and the internal write state

machine (WSM). The available commands are listed in

Table 3, their definitions are given in Table 4 and their

descriptions in Table 5. Program and erase algorithms

are automated by an on-chip WSM. Table 6 shows the

CSM transition states.

Once a valid PROGRAM/ERASE command is

entered, the WSM executes the appropriate algorithm,

which generates the necessary timing signals to con-

trol the device internally and accomplish the

requested operation. A command is valid only if the

exact sequence of WRITE cycles is completed. After the

WSM completes its task, the WSM status bit (SR7) (see

Table 8) is set to a logic HIGH level (1), allowing the

CSM to respond to the full command set again.

OPERATIONS

Device operations are selected by entering a stan-

dard JEDEC 8-bit command code with conventional

microprocessor timings into an on-chip CSM through

I/Os DQ0–DQ7. The number of bus cycles required to

activate a command is typically one or two. The first

operation is always a WRITE. Control signals CE# and

WE# must be at a logic LOW level (VIL), and OE# and

RP# must be at logic HIGH (VIH). The second opera-

tion, when needed, can be a WRITE or a READ

depending upon the command. During a READ opera-

tion, control signals CE# and OE# must be at a logic

LOW level (Vil), and WE# and RP# must be at logic

HIGH (VIH).

Table 7 illustrates the bus operations for all the

modes: write, read, reset, standby, and output disable.

When the device is powered up, internal reset cir-

cuitry initializes the chip to a read array mode of oper-

ation. Changing the mode of operation requires that a

command code be entered into the CSM. An on-chip

status register is available. The status register allows

the monitoring of the progress of various operations

that can take place on a memory. The status register is

interrogated by entering a READ STATUS REGISTER

command onto the CSM (cycle 1) and reading the reg-

ister data on I/Os DQ0–DQ7 (cycle 2). Status register

bits SR0–SR7 correspond to DQ0–DQ7 (see Table 8).

Command Definition

Once a specific command code has been entered,

the WSM executes an internal algorithm, generating

the necessary timing signals to program, erase, and

verify data. See Table 4 for the CSM command defini-

tions and data for each of the bus cycles.

Table 3: Command State Machine Codes For

Device Mode Selection

COMMAND DQ0–DQ7

40h/10h

20h

50h

60h

70h

90h

98h

B0h

C0h

D0h

FFh

CODE ON DEVICE MODE

Program setup/alternate program setup

Block erase setup

Clear status register

Protection configuration setup

Read status register

Read protection configuration register

Read query

Program/erase suspend

Protection register program/lock

Program/erase resume – erase confirm

Read array

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

MT28F320A18_3.fm - Rev. 3, Pub. 9/2002

7

©2002, Micron Technology Inc.

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